4e06c1a779
Add clock controller bindings for RPMHCC/GCC/CAMCC/VIDEOCC/DISPCC/GPUCC on Parrot Platform. Change-Id: Iaa50f7bf3758ea5fba1fe4249b7b16173320521d Signed-off-by: Chetan C R <quic_cchinnad@quicinc.com>
82 lines
2.6 KiB
YAML
82 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-parrot.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Global Clock & Reset Controller
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Global clock control module which supports the clocks, resets and
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power domains on Parrot.
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See also:
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- dt-bindings/clock/qcom,gcc-parrot.h
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properties:
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compatible:
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const: qcom,parrot-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source (Optional clock)
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- description: UFS Phy Rx symbol 0 clock source (Optional clock)
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- description: UFS Phy Rx symbol 1 clock source (Optional clock)
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- description: UFS Phy Tx symbol 0 clock source (Optional clock)
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- description: USB3 Phy wrapper pipe clock source (Optional clock)
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minItems: 2
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clock-names:
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items:
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- const: bi_tcxo
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- const: sleep_clk
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- const: pcie_0_pipe_clk # Optional clock
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- const: ufs_phy_rx_symbol_0_clk # Optional clock
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- const: ufs_phy_rx_symbol_1_clk # Optional clock
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- const: ufs_phy_tx_symbol_0_clk # Optional clock
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
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minItems: 2
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vdd_cx-supply:
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description: Phandle pointer to the vdd_cx logic rail supply
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vdd_mxa-supply:
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description: Phandle pointer to the vdd_mxa logic rail supply
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required:
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- compatible
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- clocks
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- clock-names
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allOf:
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- $ref: "qcom,gcc.yaml#"
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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gcc: clock-controller@100000 {
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compatible = "qcom,parrot-gcc", "syscon";
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reg = <0x100000 0x1f4200>;
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reg-name = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mxa-supply = <&VDD_MXA_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
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<&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>,
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<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
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<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
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clock-names = "bi_tcxo", "sleep_clk",
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"pcie_0_pipe_clk", "ufs_phy_rx_symbol_0_clk",
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"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
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"usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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