ee7d6850f6
git-subtree-dir: qcom/graphics git-subtree-mainline:2bb579edb5git-subtree-split:96de6303a2
117 lines
4.3 KiB
Plaintext
117 lines
4.3 KiB
Plaintext
Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU)
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Required properties:
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- compatible :
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- "qcom,gpu-gmu"
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- "qcom,gpu-gmu-hwsched"
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- "qcom,gpu-rgmu"
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- "qcom,gen7-gmu"
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- "qcom,gen7-gmu-hwsched"
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- reg: Specifies the GMU register base address and size.
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- reg-names: Resource names used for the physical address
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and length of GMU registers.
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- interrupts: Interrupt mapping for GMU and HFI IRQs.
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- interrupt-names: String property to describe the name of each interrupt.
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Bus Scaling Data:
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qcom,msm-bus,name: String property to describe the name of bus client.
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qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
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qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
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qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
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<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
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<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
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<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
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This property is a series of all vectors for all Bus Scaling Usecases.
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Each set of vectors for each usecase describes bandwidth votes for a combination
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of src/dst ports. The driver will set the desired use case based on the selected
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power level and the desired bandwidth vote will be registered for the port pairs.
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GMU GDSC/regulators:
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- regulator-names: List of regulator name strings
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- vddcx-supply: Phandle for vddcx regulator device node.
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- vdd-supply: Phandle for vdd regulator device node.
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- clock: List of clocks to be used for GMU register access and DCVS. See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for information about the format. For each clock specified
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here, there must be a corresponding entry in clock-names
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(see below).
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- clock-names: List of clock names corresponding to the clocks specified in
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the "clocks" property (above). See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for more info. Currently GMU required these clock names:
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"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",
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"rbcpr_clk"
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- qcom,gmu-freq-table: List of frequencies the GMU clock can run at with their corresponding
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voltage levels.
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- List of sub nodes, one for each of the translation context banks needed
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for GMU to access system memory in different operating mode. Currently
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supported names are:
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- gmu_user: used for GMU 'user' mode address space.
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- gmu_kernel: used for GMU 'kernel' mode address space.
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Each sub node has the following required properties:
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- compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb"
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- iommus : Specifies the SID's used by this context bank, this
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needs to be <kgsl_smmu SID> pair, kgsl_smmu is the string
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parsed by iommu driver to match this context bank with the
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kgsl_smmu device defined in iommu device tree. On targets
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where the msm iommu driver is used rather than the arm smmu
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driver, this property may be absent.
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- qcom,ipc-core: <baseAddr size>
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baseAddr - base address of the IPC region
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size - size of the IPC region
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- qcom,soccp-controller: Phandle of the soccp controller
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Example:
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gmu: qcom,gmu@2c6a000 {
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label = "kgsl-gmu";
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compatible = "qcom,gpu-gmu";
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reg = <0x2c6a000 0x30000>;
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reg-names = "kgsl_gmu_reg";
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interrupts = <0 304 0>, <0 305 0>;
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interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq";
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qcom,msm-bus,name = "cnoc";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 10036 0 0>, // CNOC off
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<26 10036 0 100>; // CNOC on
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regulator-name = "vddcx", "vdd";
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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clocks = <&clock_gpugcc clk_gcc_gmu_clk>,
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<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
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<&clock_gpucc GPU_CC_CXO_CLK>,
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<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gpucc GPU_CC_RBCPR_CLK>;
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clock-names = "gmu_clk", "ahb_clk", "cxo_clk",
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"axi_clk", "memnoc_clk", "rbcpr_clk";
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qcom,gmu-freq-table = <200000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
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<500000000 RPMH_REGULATOR_LEVEL_SVS>;
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gmu_user: gmu_user {
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compatible = "qcom,smmu-gmu-user-cb";
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iommus = <&kgsl_smmu 4>;
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};
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gmu_kernel: gmu_kernel {
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compatible = "qcom,smmu-gmu-kernel-cb";
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iommus = <&kgsl_smmu 5>;
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};
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};
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