12a89c859a
In this change adding memory region for iommu node for tuna. Change-Id: I50bc3d510bfab93bc5bfc22c2e3c44b9c450c8f1 Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
69 lines
1.7 KiB
Plaintext
69 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-tuna.h>
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#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>
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&soc {
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa600000 0x100000>;
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reg-names = "core_base";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,core-clk-rate-disconnected = <133333333>;
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dwc3_0: dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xa600000 0x0 0xd93c>;
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iommus = <&apps_smmu 0x40 0x0>;
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qcom,iommu-dma = "atomic";
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memory-region = <&dwc3_mem_region>;
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dma-coherent;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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snps,ssp-u3-u0-quirk;
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tx-fifo-resize;
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dr_mode = "otg";
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maximum-speed = "super-speed-plus";
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usb-role-switch;
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};
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};
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dwc3_mem_region: dwc3_mem_region {
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iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>,
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<&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>;
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};
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};
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