6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
43 lines
1.3 KiB
Plaintext
43 lines
1.3 KiB
Plaintext
* UCTL SATA controller glue
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UCTL is the bridge unit between the I/O interconnect (an internal bus)
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and the SATA AHCI host controller (UAHC). It performs the following functions:
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- provides interfaces for the applications to access the UAHC AHCI
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registers on the CN71XX I/O space.
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- provides a bridge for UAHC to fetch AHCI command table entries and data
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buffers from Level 2 Cache.
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- posts interrupts to the CIU.
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- contains registers that:
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- control the behavior of the UAHC
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- control the clock/reset generation to UAHC
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- control endian swapping for all UAHC registers and DMA accesses
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Properties:
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- compatible: "cavium,octeon-7130-sata-uctl"
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Compatibility with the cn7130 SOC.
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- reg: The base address of the UCTL register bank.
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- #address-cells, #size-cells, ranges and dma-ranges must be present and hold
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suitable values to map all child nodes.
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Example:
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uctl@118006c000000 {
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compatible = "cavium,octeon-7130-sata-uctl";
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reg = <0x11800 0x6c000000 0x0 0x100>;
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ranges; /* Direct mapping */
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dma-ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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sata: sata@16c0000000000 {
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compatible = "cavium,octeon-7130-ahci";
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reg = <0x16c00 0x00000000 0x0 0x200>;
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interrupt-parent = <&cibsata>;
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interrupts = <2 4>; /* Bit: 2, level */
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};
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};
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