Files
android_kernel_samsung_sm87…/qcom/ravelin-vm.dtsi
Prakash Yadachi 10436a9cce ARM: dts: msm: Update static gpii mask for ravelin-vm
Currently, the static gpii mask for gpi_dma0 is incorrectly
set to 0x20, which is resulting in i2c read failure.

To prevent this i2c read failure, the static gpii mask
value for gpi_dma0 needs to be updated to 0x40.

'Fixes: 5d97d9eda4527 ("ARM: dts: msm: Add memory and clock
support for vm ravelin")'.

Change-Id: I4f1785b1f1544e436e511af2622ccf365f3cbcfe
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-12-04 01:00:35 -08:00

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "waipio-vm.dtsi"
#include <dt-bindings/clock/qcom,gcc-parrot.h>
/ {
qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>;
interrupt-parent = <&vgic>;
qcom,vm-config {
iomemory-ranges = <0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0
0x0 0x0928000 0x0 0x0928000 0x0 0x4000 0x0
0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1>;
gic-irq-ranges = <282 282>; /* PVM->SVM IRQ transfer */
vdevices {
gvsock-message-queue-pair {
status = "disabled";
};
};
};
};
&soc {
/delete-node/ interrupt-controller@17100000;
qcom,spmi@c42d000 {
status = "disabled";
};
gcc: clock-controller@100000 {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
vgic: interrupt-controller@17200000 {
compatible = "arm,gic-v3";
interrupt-controller;
#interrupt-cells = <0x3>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17200000 0x10000>, /* GICD */
<0x17260000 0x100000>; /* GICR * 8 */
};
tlmm: pinctrl@f000000 {
compatible = "qcom,ravelin-vm-tlmm";
gpios = /bits/ 16 <92 93>;
};
tlmm-vm-mem-access {
tlmm-vm-gpio-list = <&tlmm 92 0 &tlmm 93 0>;
};
apps-smmu@15000000 {
qcom,actlr =
/* Display and camera clients, +0 PF */
<0x1900 0x3F 0x1>,
<0x1800 0xFF 0x1>,
<0x800 0x7FF 0x1>,
/* For video clients, +3 PF */
<0x1980 0x3F 0x103>;
};
/delete-node/ qup_common_iommu_group;
/delete-node/ qcom,qupv3_0_geni_se@9c0000;
/delete-node/ qcom,gpi-dma@900000;
/delete-node/ i2c@990000;
/delete-node/ spi@990000;
qup_iommu_group: qup_common_iommu_group {
iommu-addresses = <&gpi_dma0 0x00000000 0x00020000>,
<&qupv3_0 0x00000000 0x00020000>;
};
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x900000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x178 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x40>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <2>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x9c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x178 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* Legacy Touch over I2C */
qupv3_se1_i2c: i2c@984000 {
compatible = "qcom,i2c-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma0 0 1 3 64 0xe>,
<&gpi_dma0 1 1 3 64 0xe>;
dma-names = "tx", "rx";
qcom,le-vm;
status = "disabled";
};
qupv3_se1_spi: spi@984000 {
compatible = "qcom,spi-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma0 0 1 1 64 0xe>,
<&gpi_dma0 1 1 1 64 0xe>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,le-vm;
status = "disabled";
};
};
};