63ca55d666
Add support for cpufreq_hw, clock controller nodes and their corresponding gdsc's for SM6150. Change-Id: I7d64cbe80eb7f10277acce0a0c91fb788c3c99dc Signed-off-by: Chintan Kothari <quic_ckothari@quicinc.com>
196 lines
4.7 KiB
Plaintext
196 lines
4.7 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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/* GDSCs in Global CC */
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emac_gdsc: qcom,gdsc@106004 {
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compatible = "qcom,gdsc";
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reg = <0x106004 0x4>;
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regulator-name = "emac_gdsc";
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status = "disabled";
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};
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pcie_0_gdsc: qcom,gdsc@16b004 {
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compatible = "qcom,gdsc";
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reg = <0x16b004 0x4>;
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regulator-name = "pcie_0_gdsc";
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status = "disabled";
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};
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ufs_phy_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,gdsc";
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reg = <0x177004 0x4>;
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regulator-name = "ufs_phy_gdsc";
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status = "disabled";
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};
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usb20_sec_gdsc: qcom,gdsc@1a6004 {
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compatible = "qcom,gdsc";
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reg = <0x1a6004 0x4>;
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regulator-name = "usb20_sec_gdsc";
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status = "disabled";
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};
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usb30_prim_gdsc: qcom,gdsc@10f004 {
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compatible = "qcom,gdsc";
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reg = <0x10f004 0x4>;
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regulator-name = "usb30_prim_gdsc";
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 {
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compatible = "qcom,gdsc";
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reg = <0x17d040 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 {
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compatible = "qcom,gdsc";
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reg = <0x17d044 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 {
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compatible = "qcom,gdsc";
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reg = <0x17d048 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c {
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compatible = "qcom,gdsc";
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reg = <0x17d04c 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
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compatible = "qcom,gdsc";
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reg = <0x17d050 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 {
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compatible = "qcom,gdsc";
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reg = <0x17d054 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
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compatible = "qcom,gdsc";
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reg = <0x17d058 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* GDSCs in Camera CC */
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titan_top_gdsc: qcom,gdsc@ad0b134 {
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compatible = "qcom,gdsc";
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reg = <0xad0b134 0x4>;
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regulator-name = "titan_top_gdsc";
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status = "disabled";
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};
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bps_gdsc: qcom,gdsc@ad06004 {
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compatible = "qcom,gdsc";
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reg = <0xad06004 0x4>;
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regulator-name = "bps_gdsc";
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parent-supply = <&titan_top_gdsc>;
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status = "disabled";
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};
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ife_0_gdsc: qcom,gdsc@ad09004 {
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compatible = "qcom,gdsc";
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reg = <0xad09004 0x4>;
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regulator-name = "ife_0_gdsc";
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parent-supply = <&titan_top_gdsc>;
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status = "disabled";
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};
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ife_1_gdsc: qcom,gdsc@ad0a004 {
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compatible = "qcom,gdsc";
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reg = <0xad0a004 0x4>;
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regulator-name = "ife_1_gdsc";
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parent-supply = <&titan_top_gdsc>;
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status = "disabled";
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};
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ipe_0_gdsc: qcom,gdsc@ad07004 {
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compatible = "qcom,gdsc";
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reg = <0xad07004 0x4>;
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regulator-name = "ipe_0_gdsc";
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parent-supply = <&titan_top_gdsc>;
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status = "disabled";
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};
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/* GDSCs in Display CC */
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mdss_core_gdsc: qcom,gdsc@af03000 {
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compatible = "qcom,gdsc";
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reg = <0xaf03000 0x4>;
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regulator-name = "mdss_core_gdsc";
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qcom,support-hw-trigger;
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status = "disabled";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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};
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/* GDSCs in Graphics CC */
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gpu_cx_hw_ctrl: syscon@5091540 {
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compatible = "syscon";
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reg = <0x5091540 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@509106c {
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compatible = "qcom,gdsc";
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reg = <0x509106c 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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qcom,clk-dis-wait-val = <8>;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@509100c {
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compatible = "qcom,gdsc";
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reg = <0x509100c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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status = "disabled";
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};
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/* GDSCs in Video CC */
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vcodec0_gdsc: qcom,gdsc@ab00874 {
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compatible = "qcom,gdsc";
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reg = <0xab00874 0x4>;
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regulator-name = "vcodec0_gdsc";
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status = "disabled";
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};
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venus_gdsc: qcom,gdsc@ab00814 {
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compatible = "qcom,gdsc";
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reg = <0xab00814 0x4>;
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regulator-name = "venus_gdsc";
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status = "disabled";
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};
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};
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