3c46ebee9d
Modify SMMU register field format as per the parent SoC address and size cells. Change-Id: Ifce3e103601a82b1b9f6295d6abef826f917b0fc Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
118 lines
3.2 KiB
Plaintext
118 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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apps_smmu: apps-smmu@15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x0 0x15000000 0x0 0x40000>;
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#iommu-cells = <2>;
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qcom,use-3-lvl-tables;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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dma-coherent;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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anoc_1_qtb: anoc_1_qtb@1680000 {
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compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
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reg = <0x1680000 0x1000>;
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qcom,stream-id-range = <0x0 0x400>;
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qcom,iova-width = <36>;
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qcom,num-qtb-ports = <1>;
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};
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ipa_qtb: ipa_qtb@1688000 {
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compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
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reg = <0x1688000 0x1000>;
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qcom,stream-id-range = <0x400 0x400>;
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qcom,iova-width = <41>;
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qcom,num-qtb-ports = <1>;
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};
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pcie_qtb: pcie_qtb@16d0000 {
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compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
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reg = <0x16d0000 0x1000>;
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qcom,stream-id-range = <0x800 0x400>;
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qcom,iova-width = <36>;
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qcom,num-qtb-ports = <1>;
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qcom,opt-out-tbu-halting;
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};
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};
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dma_dev {
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compatible = "qcom,iommu-dma";
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memory-region = <&system_cma>;
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};
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iommu_test_device {
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compatible = "qcom,iommu-debug-test";
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usecase0_apps {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x3e0 0x0>;
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};
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usecase1_apps_fastmap {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x3e0 0x0>;
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qcom,iommu-dma = "fastmap";
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};
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usecase2_apps_atomic {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x3e0 0x0>;
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qcom,iommu-dma = "atomic";
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};
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usecase3_apps_dma {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x3e0 0x0>;
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dma-coherent;
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};
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usecase4_apps_secure {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x3e0 0x0>;
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qcom,iommu-vmid = <0x2d>; /* VMID_TUIVM */
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};
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};
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};
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