e2fe040035
Add bindings for thermal devices on Sun Soc, converted to YAML format. Change-Id: Ie5c39b55055c8f4e2a581128afdc45399cfb0c31 Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
105 lines
3.6 KiB
YAML
105 lines
3.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/thermal/qti-lmh-dcvs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Limits Management Hardware DCVS Cooling Device
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maintainers:
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- Rashid Zafar <quic_rzafar@quicinc.com>
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description: |
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The LMH-DCVS block is a hardware IP for every CPU cluster, to handle quick
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changes in thermal limits. The hardware responds to thermal variation amongst
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the CPUs in the cluster by requesting limits on the clock frequency and
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voltage on the OSM hardware.
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The LMH DCVS driver exports a virtual sensor that can be used to set the
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thermal limits on the hardware. LMH DCVS driver can be a platform CPU Cooling
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device, which registers with the CPU cooling device interface. All CPU device
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nodes should reference the corresponding LMH DCVS hardware in device tree.
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CPUs referencing the same LMH DCVS node will be associated with the
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corresponding cooling device as related CPUs.
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properties:
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compatible:
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const: qcom,msm-hw-limits
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reg:
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maxItems: 2
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description: |
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<a, b> where 'a' is the starting register address of the OSM/LLM
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and 'b' is the size of OSM/LLM address space. The
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register space in index 0 should be LLM and index 1
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should be OSM.
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interrupts:
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maxItems: 1
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description: |
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Should specify interrupt information about the debug
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interrupt generated by the LMH DCVSh hardware. LMH
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DCVSh hardware will generate this interrupt whenever
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it makes a new CPU DCVS decision.
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qcom,affinity:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Should specify the cluster affinity this hardware corresponds to.
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isens_vref_0p8-supply:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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Should specify the phandle of the vref regulator used by
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the isens hardware. This active only regulator will be
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enabled by LMH DCVSh. Isens hardware needs 1.8v and
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0.8v supply regulators.
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isens_vref_1p8-supply:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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Should specify the phandle of the vref regulator used by
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the isens hardware. This active only regulator will be
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enabled by LMH DCVSh. Isens hardware needs 1.8v and
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0.8v supply regulators.
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isens-vref-0p8-settings:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Should specify the min voltage(uV), max voltage(uV) and
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max load(uA) for the isens vref regulator. This
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property is valid only if there is valid entry for
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isens_vref_0p8-supply.
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isens-vref-1p8-settings:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Should specify the min voltage(uV), max voltage(uV) and
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max load(uA) for the isens vref regulator. This
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property is valid only if there is valid entry for
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isens_vref_1p8-supply.
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qcom,no-cooling-device-register:
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type: boolean
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description: |
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Should define this property if this driver doesn't need
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to register CPU cooling devices with thermal framework.
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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qcom,limits-dcvs {
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compatible = "qcom,msm-hw-limits";
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isens_vref_0p8-supply = <&pm_v8_l1_ao>;
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isens-vref-0p8-settings = <880000 880000 30000>;
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isens_vref_1p8-supply = <&pm_v8_l3_ao>;
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isens-vref-1p8-settings = <1200000 1200000 8000>;
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};
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