d66bf7fb83
Change https://lore.kernel.org/all/20230525113034.46880-1-tony@atomide.com registers serial core controller as a child of msm uart device. Since child should suspend first, due to the child's auto suspend delay (SERIAL_PORT_AUTOSUSPEND_DELAY_MS), additional 500msecs delay is added during msm_geni_serial_runtime_suspend. Added new optional dtsi property 'qcom,suspend-ignore-children' which when set ignores dependencies on children by PM framework, this helps to exit quickly from msm_geni_serial_runtime_suspend and save power. Change-Id: I36b239cf19293ee7b1ebecf32cdd0ad0749dbca1 Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
107 lines
2.8 KiB
YAML
107 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-msm.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Technologies, Inc. Serial UART for GENI based cores
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maintainers:
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- Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
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allOf:
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- $ref: /schemas/serial/serial.yaml#
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properties:
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compatible:
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enum:
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- qcom,msm-geni-serial-hs
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- qcom,msm-geni-console
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clocks:
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maxItems: 1
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clock-names:
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const: se-clk
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interconnects:
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maxItems: 3
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interconnect-names:
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items:
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- const: qup-core
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- const: qup-config
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- const: qup-memory
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interrupts:
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description: first irq for UART core & second irq for host wake up
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maxItems: 2
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operating-points-v2: true
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pinctrl-0: true
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pinctrl-1: true
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pinctrl-2: true
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pinctrl-3: true
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: active
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- const: sleep
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- const: shutdown
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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# Optional property
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qcom,suspend-ignore-children:
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type: boolean
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description: When set ignores dependencies on children by PM framework
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- reg
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- qcom,wakeup-byte
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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qupv3_se14_4uart: qcom,qup_uart@898000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x898000 0x4000>;
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reg-names = "se_phys";
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interrupts = <&intc GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 27 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
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<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
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<&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
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pinctrl-1 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
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<&qupv3_se14_tx>, <&qupv3_se14_rx>;
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pinctrl-2 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
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<&qupv3_se14_tx>, <&qupv3_se14_default_rx>;
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pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
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<&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
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qcom,wakeup-byte = <0xFD>;
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qcom,suspend-ignore-children;
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};
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...
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