32a0054a70
Remove the qcom,cesta-l1sub-timeout-ext-int property as its no
longer required due to recent changes in the pcie driver using the
change commit b53d4aa20ee7 ("pci: msm: Add support to enable
PCIE CESTA clkreq config").
Initially this property was intended to be used to enable the BIT(3):
PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN field of
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register for platforms where CESTA
is enabled and the platform is not pineapple.
Currently the pcie driver will by default set this BIT(3) when CESTA is
enabled and the qcom,pcie-clkreq-offset property is present. Since the
qcom,pcie-clkreq-offset property will not be present when CESTA
is enabled on pineapple, pcie driver will not touch the
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register.
Pcie driver will set only the BIT(0) PARF_CESTA_CLKREQ_SEL field when
qcom,pcie-clkreq-offset property is present and CESTA is not present
which is the case of pineapple platform when CESTA is enabled. And
this case is also taken care of by the pcie driver without the need
for qcom,pcie-clkreq-offset property.
Below are the required cases that needs to be taken care of by the
pcie driver.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | BIT(0) set | BIT(3) set | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | need to set| need to set| non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | set by | Not | pineapple |
| | default | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | need to | Not | pineapple |
| | unset | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Above mentioned cases are taken care by using the qcom,pcie-clkreq-offset
property in the following way.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | qcom,pcie-clkreq-offset | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | YES | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | NO | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | YES | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Change-Id: I1bc4985be0080d295153233b0d5d4ce07e006818
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
1181 lines
37 KiB
YAML
1181 lines
37 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-msm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) MSM PCI express root complex
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maintainers:
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- Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
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description:
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Qualcomm Technologies, Inc MSM PCIe root complex controller is based
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on the Synopsys DesignWare PCIe IP.
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properties:
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compatible:
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const: qcom,pci-msm
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reg:
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minItems: 6
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items:
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- description: PCIe MSM specific (parf) registers.
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- description: PCIe Physical layer (phy) registers.
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- description: DesignWare PCIe core (dm_core) registers.
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- description: External local bus interface (elbi) registers.
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- description: Internal address translation unit (iatu) registers.
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- description: PCIe device configuration space (conf) registers.
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- description: PCIe state manager (pcie_sm) registers.
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- description: PCIe clock scheme (tcsr) registers.
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- description: PCIe RUMI (rumi) registers.
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reg-names:
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minItems: 6
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items:
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- const: parf
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- const: phy
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- const: dm_core
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- const: elbi
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- const: iatu
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- const: conf
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- const: pcie_sm
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- const: tcsr
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- const: rumi
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: PCIe instance index.
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linux,pci-domain:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: PCI domain ID which is identifies the host controller.
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'#address-cells':
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const: 3
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'#size-cells':
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const: 2
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ranges:
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minItems: 1
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maxItems: 2
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interrupts:
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minItems: 3
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maxItems: 15
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interrupt-names:
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minItems: 1
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items:
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- const: int_global_int
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- const: int_a
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- const: int_b
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- const: int_c
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- const: int_d
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interrupt-map-mask:
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description: Specified in the designware-pcie.txt
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$ref: /schemas/types.yaml#/definitions/uint32-array
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interrupt-map:
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description: Specified in the designware-pcie.txt
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$ref: /schemas/types.yaml#/definitions/uint32-array
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"#interrupt-cells":
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const: 1
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msi-map:
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description:
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Maps a Requester ID to an MSI controller and associated msi-specifier data.
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qcom,pcie-clkreq-pin:
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description: Clkreq gpio number.
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$ref: /schemas/types.yaml#/definitions/uint32
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perst-gpio:
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maxItems: 1
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description: GPIO controlled connection to PERST# signal.
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wake-gpio:
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maxItems: 1
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description: GPIO controlled connection to WAKE# signal.
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qcom,bw-scale:
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description: List of CX voltage corner and rate change clock frequency pair for each PCIe GEN speed.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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interconnects:
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items:
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- description: PCIe to DDR icc path handle.
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interconnect-names:
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items:
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- const: icc_path
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gdsc-core-vdd-supply:
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description: A phandle to the core gdsc power supply.
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gdsc-phy-vdd-supply:
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description: A phandle to the phy gdsc power supply.
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vreg-1p2-supply:
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description: A phandle to the 1.2v power supply.
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vreg-0p9-supply:
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description: A phandle to the 0.9v power supply.
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vreg-cx-supply:
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description: A phandle to the cx power supply.
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vreg-mx-supply:
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description: A phandle to the mx power supply.
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vreg-qref-supply:
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description: A phandle to the qref power supply.
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qcom,vreg-1p2-voltage-level:
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description: Array containing the min, max supported voltage and current for 1.2v power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vreg-0p9-voltage-level:
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description: Array containing the min, max supported voltage and current for 0.9v power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vreg-cx-voltage-level:
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description: Array containing the min, max supported voltage and current for cx power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vreg-mx-voltage-level:
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description: Array containing the min, max supported voltage and current for mx power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vreg-qref-voltage-level:
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description: Array containing the min, max supported voltage and current for qref power supply.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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clocks:
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description: Phandles to the clocks.
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pcie_pipe_clk - Core clock for PIPE, generated by PHY
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pcie_ref_clk_src - REFCLK source (XO clock).
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pcie_aux_clk - Auxilary clock for power management control.
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pcie_cfg_ahb_clk - Ahb slave interface clock, configuration bus clock.
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pcie_mstr_axi_clk - Axi master interface clock, system bus clock.
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pcie_slv_axi_clk - Axi slave + DBI slave interface clock, system bus clock.
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pcie_clkref_en - TCSR reference clock.
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pcie_slv_q2a_axi_clk - Slave AXI clock.
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pcie_rate_change_clk - This clock varies based on the PCIe Gen speed, needed by PHY.
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gcc_ddrss_pcie_sf_qtb_clk - Needed for accessing the ddr subsystem.
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pcie_aggre_noc_axi_clk - AGNOC axi clock.
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gcc_cnoc_pcie_sf_axi_clk - This is needed for CPU to access the PCIe DBI registers.
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pcie_pipe_clk_mux - mux for the PIPE clock, choose between (XO/PHY).
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pcie_pipe_clk_ext_src - external source clock (PHY) for the PIPE clock.
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pcie_phy_aux_clk (not needed for Gen3 controller) - Auxilary phy clock for L1 substates.
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minItems: 1
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maxItems: 15
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clock-names:
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description: Names of the clocks.
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minItems: 1
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maxItems: 15
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anyOf:
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- items:
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- const: pcie_pipe_clk
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- const: pcie_ref_clk_src
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- const: pcie_aux_clk
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- const: pcie_cfg_ahb_clk
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- const: pcie_mstr_axi_clk
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- const: pcie_slv_axi_clk
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- const: pcie_clkref_en
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- const: pcie_slv_q2a_axi_clk
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- const: pcie_rate_change_clk
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- const: gcc_ddrss_pcie_sf_qtb_clk
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- const: pcie_aggre_noc_axi_clk
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- const: gcc_cnoc_pcie_sf_axi_clk
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- const: pcie_pipe_clk_mux
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- const: pcie_pipe_clk_ext_src
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- const: pcie_phy_aux_clk
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- items:
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- const: pcie_pipe_clk
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- const: pcie_ref_clk_src
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- const: pcie_aux_clk
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- const: pcie_cfg_ahb_clk
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- const: pcie_mstr_axi_clk
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- const: pcie_slv_axi_clk
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- const: pcie_clkref_en
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- const: pcie_slv_q2a_axi_clk
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- const: pcie_rate_change_clk
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- const: gcc_ddrss_pcie_sf_qtb_clk
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- const: pcie_aggre_noc_axi_clk
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- const: gcc_cnoc_pcie_sf_axi_clk
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- const: pcie_pipe_clk_mux
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- const: pcie_pipe_clk_ext_src
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- items:
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- const: pcie_pipe_clk
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- items:
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- const: pcie_ref_clk_src
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- items:
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- const: pcie_aux_clk
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- items:
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- const: pcie_cfg_ahb_clk
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- items:
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- const: pcie_mstr_axi_clk
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- items:
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- const: pcie_slv_axi_clk
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- items:
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- const: pcie_clkref_en
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- items:
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- const: pcie_slv_q2a_axi_clk
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- items:
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- const: pcie_rate_change_clk
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- items:
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- const: gcc_ddrss_pcie_sf_qtb_clk
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- items:
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- const: pcie_aggre_noc_axi_clk
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- items:
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- const: gcc_cnoc_pcie_sf_axi_clk
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- items:
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- const: pcie_pipe_clk_mux
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- items:
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- const: pcie_pipe_clk_ext_src
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- items:
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- const: pcie_phy_aux_clk
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qcom,pcie-clock-frequency:
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description: List of frequencies for the clocks.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 15
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clock-suppressible:
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description: List describing if the clock is a suppressible clock or not.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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max-clock-frequency-hz:
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description: List describing the each PCIe clock frequency.
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resets:
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minItems: 2
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items:
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- description: A phandle to the PCIe controller reset.
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- description: A phandle to the PCIe PHY reset.
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- description: A phandle to the PCIe link down reset.
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- description: A phandle to the PCIe com phy reset.
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reset-names:
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description: Names of the resets. The names are as below.
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minItems: 2
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maxItems: 4
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oneOf:
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- items:
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- const: pcie_0_core_reset
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- const: pcie_0_phy_reset
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- items:
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- const: pcie_1_core_reset
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- const: pcie_1_phy_reset
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- const: pcie_1_link_down_reset
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- const: pcie_1_phy_nocsr_com_phy_reset
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dma-coherent: true
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qcom,smmu-sid-base:
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description: Base SID for PCIe.
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$ref: /schemas/types.yaml#/definitions/uint32
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iommu-map:
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description: As described in the pci-iommu.txt.
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maxItems: 2
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qcom,boot-option:
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description: Controls the PCIe driver boot sequence. When BIT(0) is set,
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driver will not start enumeration during its probe and client
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will control when the enumeration should happen. When BIT(1)
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is set, PCIe driver will not start enumeration when it
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receives a WAKE interrupt.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,aux-clk-freq:
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description: This sets the aux clock frequency value.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,drv-supported:
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description: This is a boolean flag that indicates drv is supported or not.
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type: boolean
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qcom,drv-l1ss-timeout-us:
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description: This timeout determines when the PCIe resources will be turned
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off after the PCIe link enters l1ss. The default value is 100ms.
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qcom,l1-2-th-scale:
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description: Determines the multiplier for L1.2 LTR threshold value.
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- 0 1ns
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- 1 32ns
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- 2 1us
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- 3 32us
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- 4 1ms
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- 5 32ms
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3, 4, 5]
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qcom,l1-2-th-value:
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description: L1.2 LTR threshold value to be multipled with scale to
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define L1.2 latency tolerance reporting (LTR).
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,slv-addr-space-size:
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description: Memory block size dedicated to PCIe root complex.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,ep-latency:
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description: The latency(ms) between when PCIe PHY is up and PERST is
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de-asserted. This guarantees the 100MHz clock is available
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for the PCIe devices.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,num-parf-testbus-sel:
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description: Testbus selection number/index in parf register space.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,config-recovery:
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description: This will notify the PCIe client that link is down during
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the PCIe enumeration if the config spac read returns all Fs.
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type: boolean
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qcom,pcie-phy-ver:
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description: States the PCIe PHY HSR version.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,phy-status-offset:
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description: Offset from PCIe PHY base to check the PCIe PHY status.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,phy-status-bit:
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description: BIT to check PCIe PHY status.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,phy-power-down-offset:
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description: Offset from PCIe PHY base to control PHY power state.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,phy-sequence:
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description: PCIe PHY initialization sequence.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,parf-debug-reg:
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description: Debug property to dump parf registers.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,dbi-debug-reg:
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description: Debug property to dump parf registers.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,phy-debug-reg:
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description: Debug property to dump parf registers.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,pcie-sm-branch-offset:
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description: Offset from PCIe state manager base to load branch sequence.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pcie-sm-start-offset:
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description: Offset from PCIe state manager base to load the sequence.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pcie-sm-seq:
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description: PCIe State Manager sequence.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,pcie-sm-branch-seq:
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description: PCIe state manager branch sequence.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,pcie-sm-debug:
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description: PCIe SM register dump offsets.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,pcie-clkreq-offset:
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description: Offset from PCIe PHY base to PCIe CESTA CLKREQ register.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,core-preset:
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description: Determines how aggressive the PCIe PHY equalization is for
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Gen3 cores. The following are recommended settings.
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short channels - 0x55555555 (default),
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long channels - 0x77777777.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,target-link-speed:
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description: This will override the max Gen speed.
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- 0x1 GEN1
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- 0x2 GEN2
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- 0x3 GEN3
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2, 3]
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qcom,link-check-max-count:
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description: Max number of retries for link training.
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Delay between each check is 5ms.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,drv-name:
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description: Direct resource vote (DRV) is supported. APPS PCIe root
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complex driver can hand off PCIe resources to another subsystem.
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This will allow APPS to enter lower power modes while keeping
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PCIe core, PHY, and link funtional. In addition, the system can
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enter CX power collapse once the DRV subsystem removes its
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PCIe votes.
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$ref: /schemas/types.yaml#/definitions/string
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qcom,use-19p2mhz-aux-clk:
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description: Set PCIe AUX clock frequency to 19.2MHz.
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type: boolean
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qcom,common-clk-en:
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description: Support common clock configuration.
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type: boolean
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qcom,clk-power-manage-en:
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description: Support clock power management.
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type: boolean
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qcom,n-fts:
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description: Number of fast training sequences sent when the link
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transitions from L0s to L0.
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$ref: /schemas/types.yaml#/definitions/uint32
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|
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qcom,no-l0s-supported:
|
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description: L0s is not supported.
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type: boolean
|
|
|
|
qcom,no-l1-supported:
|
|
description: L1 is not supported.
|
|
type: boolean
|
|
|
|
qcom,no-l1ss-supported:
|
|
description: L1 sub-state (ss) is not supported.
|
|
type: boolean
|
|
|
|
qcom,no-aux-clk-sync:
|
|
description: The AUX clock is not synchronous to the Core clock to
|
|
support l1ss.
|
|
type: boolean
|
|
|
|
qcom,wr-halt-size:
|
|
description: Exponent (base 2) that determines the data size(bytes) that
|
|
PCIe core will halt for each write.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
|
|
qcom,tlp-rd-size:
|
|
description: Determines the maximum read request size(bytes). Options are
|
|
- 0 128
|
|
- 1 256
|
|
- 2 512
|
|
- 3 1K
|
|
- 4 2K
|
|
- 5 4K
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
enum: [0, 1, 2, 3, 4, 5]
|
|
|
|
qcom,cpl-timeout:
|
|
description: Determines the timeout range PCIe root complex will send
|
|
out a completion packet if no ACK is seen for TLP. Options are
|
|
- BIT(0) 50us to 10ms
|
|
- BIT(1) 10ms to 250ms
|
|
- BIT(2) 250ms to 4s
|
|
- BIT(3) 4s to 64s
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
enum: [0, 1, 2, 3]
|
|
|
|
qcom,perst-delay-us-min:
|
|
description: Minimum allowed time(us) to sleep after asserting or
|
|
de-asserting PERST GPI.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
|
|
qcom,perst-delay-us-max:
|
|
description: Maximum allowed time(us) to sleep after asserting or
|
|
de-asserting PERST GPI.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
|
|
qcom,switch-latency:
|
|
description: The latency(ms) between when PCIe link is up and before
|
|
any device over the switch is accessed.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
|
|
qcom,eq-fmdc-t-min-phase23:
|
|
description: Minimum time in ms to remain in EQ Master Phase. The LTSSM
|
|
stays in EQ Master phase for at least this amount of time before
|
|
starting to check for convergence of the coffecients.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
|
|
20, 21, 22, 23, 24]
|
|
|
|
pcie0_rp:
|
|
description: This is the root port node (child node).
|
|
type: object
|
|
properties:
|
|
reg:
|
|
minItems: 1
|
|
required:
|
|
- reg
|
|
|
|
pcie1_rp:
|
|
description: This is the root port node (child node).
|
|
type: object
|
|
properties:
|
|
reg:
|
|
minItems: 1
|
|
required:
|
|
- reg
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- reg-names
|
|
- cell-index
|
|
- linux,pci-domain
|
|
- ranges
|
|
- device_type
|
|
- interrupts
|
|
- interrupt-names
|
|
- perst-gpio
|
|
- wake-gpio
|
|
- qcom,bw-scale
|
|
- pinctrl-names
|
|
- pinctrl-0
|
|
- pinctrl-1
|
|
- interconnect-names
|
|
- interconnects
|
|
- resets
|
|
- reset-names
|
|
- dma-coherent
|
|
|
|
allOf:
|
|
- $ref: "/schemas/pci/pci-bus.yaml#"
|
|
- if:
|
|
properties:
|
|
reg-names:
|
|
contains:
|
|
const: pcie_sm
|
|
then:
|
|
required:
|
|
- qcom,pcie-clkreq-pin
|
|
- qcom,pcie-sm-branch-offset
|
|
- qcom,pcie-sm-start-offset
|
|
- qcom,pcie-sm-seq
|
|
- qcom,pcie-sm-branch-seq
|
|
else:
|
|
required:
|
|
- clocks
|
|
- clock-names
|
|
- qcom,pcie-clock-frequency
|
|
- clock-suppressible
|
|
properties:
|
|
qcom,pcie-clkreq-pin: false
|
|
qcom,pcie-sm-branch-offset: false
|
|
qcom,pcie-sm-start-offset: false
|
|
qcom,pcie-sm-seq: false
|
|
qcom,pcie-sm-branch-seq: false
|
|
qcom,pcie-sm-debug: false
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
|
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/clock/qcom,tcsrcc-pineapple.h>
|
|
pcie0: pcie@1c00000 {
|
|
compatible = "qcom,pci-msm";
|
|
device_type = "pci";
|
|
|
|
reg = <0x01c00000 0x3000>,
|
|
<0x01c06000 0x2000>,
|
|
<0x60000000 0xf1d>,
|
|
<0x60000f20 0xa8>,
|
|
<0x60001000 0x1000>,
|
|
<0x60100000 0x100000>,
|
|
<0x01D07000 0x7000>;
|
|
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
|
|
"pcie_sm";
|
|
|
|
cell-index = <0>;
|
|
linux,pci-domain = <0>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
|
"int_d";
|
|
|
|
msi-map = <0x0 &gic_its 0x1400 0x1>,
|
|
<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
|
|
|
|
qcom,pcie-clkreq-pin = <95>;
|
|
perst-gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>;
|
|
wake-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pcie0_perst_default
|
|
&pcie0_clkreq_default
|
|
&pcie0_wake_default>;
|
|
pinctrl-1 = <&pcie0_perst_default
|
|
&pcie0_clkreq_sleep
|
|
&pcie0_wake_default>;
|
|
|
|
qcom,bw-scale = /* Gen1 */
|
|
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen2 */
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen3 */
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
100000000>;
|
|
|
|
interconnect-names = "icc_path";
|
|
interconnects = <&pcie_noc MASTER_PCIE_0_PCIE_CRM_HW_0
|
|
&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;
|
|
|
|
gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
|
|
clocks = <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
|
|
clock-names = "gcc_cnoc_pcie_sf_axi_clk";
|
|
qcom,pcie-clock-frequency = <0>;
|
|
clock-suppressible = <1>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_BCR>,
|
|
<&gcc GCC_PCIE_0_PHY_BCR>;
|
|
reset-names = "pcie_0_core_reset",
|
|
"pcie_0_phy_reset";
|
|
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1400>;
|
|
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
|
|
<0x100 &apps_smmu 0x1401 0x1>;
|
|
|
|
qcom,boot-option = <0x1>;
|
|
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
|
qcom,drv-supported;
|
|
qcom,drv-l1ss-timeout-us = <5000>;
|
|
qcom,l1-2-th-scale = <2>;
|
|
qcom,l1-2-th-value = <150>;
|
|
qcom,slv-addr-space-size = <0x4000000>;
|
|
qcom,ep-latency = <10>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
qcom,config-recovery;
|
|
|
|
qcom,pcie-phy-ver = <104>;
|
|
qcom,phy-status-offset = <0x214>;
|
|
qcom,phy-status-bit = <6>;
|
|
qcom,phy-power-down-offset = <0x240>;
|
|
|
|
qcom,phy-sequence = <0x0240 0x03 0x0
|
|
0x00c0 0x01 0x0
|
|
0x00cc 0x62 0x0
|
|
0x00d0 0x02 0x0
|
|
0x0060 0xf8 0x0
|
|
0x0064 0x01 0x0
|
|
0x0000 0x93 0x0
|
|
0x0004 0x01 0x0
|
|
0x00e0 0x90 0x0
|
|
0x00e4 0x82 0x0
|
|
0x00f4 0x07 0x0
|
|
0x0070 0x02 0x0
|
|
0x0010 0x02 0x0
|
|
0x0074 0x16 0x0
|
|
0x0014 0x16 0x0
|
|
0x0078 0x36 0x0
|
|
0x0018 0x36 0x0
|
|
0x0110 0x08 0x0
|
|
0x00bc 0x0a 0x0
|
|
0x0120 0x42 0x0
|
|
0x0080 0x04 0x0
|
|
0x0084 0x0d 0x0
|
|
0x0020 0x0a 0x0
|
|
0x0024 0x1a 0x0
|
|
0x0088 0x41 0x0
|
|
0x0028 0x34 0x0
|
|
0x0090 0xab 0x0
|
|
0x0094 0xaa 0x0
|
|
0x0098 0x01 0x0
|
|
0x0030 0x55 0x0
|
|
0x0034 0x55 0x0
|
|
0x0038 0x01 0x0
|
|
0x0140 0x14 0x0
|
|
0x0164 0x34 0x0
|
|
0x003c 0x01 0x0
|
|
0x001c 0x04 0x0
|
|
0x0174 0x16 0x0
|
|
0x01bc 0x0f 0x0
|
|
0x0170 0xa0 0x0
|
|
0x11a4 0x38 0x0
|
|
0x10dc 0x11 0x0
|
|
0x1160 0xbf 0x0
|
|
0x1164 0xbf 0x0
|
|
0x1168 0xb7 0x0
|
|
0x116c 0xea 0x0
|
|
0x115c 0x3f 0x0
|
|
0x1174 0x5c 0x0
|
|
0x1178 0x9c 0x0
|
|
0x117c 0x1a 0x0
|
|
0x1180 0x89 0x0
|
|
0x1170 0xdc 0x0
|
|
0x1188 0x94 0x0
|
|
0x118c 0x5b 0x0
|
|
0x1190 0x1a 0x0
|
|
0x1194 0x89 0x0
|
|
0x10cc 0x00 0x0
|
|
0x1008 0x09 0x0
|
|
0x1014 0x05 0x0
|
|
0x104c 0x08 0x0
|
|
0x1050 0x08 0x0
|
|
0x10d8 0x0f 0x0
|
|
0x1118 0x1c 0x0
|
|
0x10f8 0x07 0x0
|
|
0x11f8 0x08 0x0
|
|
0x1600 0x00 0x0
|
|
0x0e84 0x15 0x0
|
|
0x0e90 0x3f 0x0
|
|
0x0ee4 0x02 0x0
|
|
0x0e40 0x09 0x0
|
|
0x0e3c 0x15 0x0
|
|
0x19a4 0x38 0x0
|
|
0x18dc 0x11 0x0
|
|
0x1960 0xbf 0x0
|
|
0x1964 0xbf 0x0
|
|
0x1968 0xb7 0x0
|
|
0x196c 0xea 0x0
|
|
0x195c 0x3f 0x0
|
|
0x1974 0x5c 0x0
|
|
0x1978 0x9c 0x0
|
|
0x197c 0x1a 0x0
|
|
0x1980 0x89 0x0
|
|
0x1970 0xdc 0x0
|
|
0x1988 0x94 0x0
|
|
0x198c 0x5b 0x0
|
|
0x1990 0x1a 0x0
|
|
0x1994 0x89 0x0
|
|
0x18cc 0x00 0x0
|
|
0x1808 0x09 0x0
|
|
0x1814 0x05 0x0
|
|
0x184c 0x08 0x0
|
|
0x1850 0x08 0x0
|
|
0x18d8 0x0f 0x0
|
|
0x1918 0x1c 0x0
|
|
0x18f8 0x07 0x0
|
|
0x19f8 0x08 0x0
|
|
0x1684 0x15 0x0
|
|
0x1690 0x3f 0x0
|
|
0x16e4 0x02 0x0
|
|
0x1640 0x09 0x0
|
|
0x163c 0x15 0x0
|
|
0x02dc 0x05 0x0
|
|
0x0388 0x77 0x0
|
|
0x0398 0x0b 0x0
|
|
0x06a4 0x1e 0x0
|
|
0x06f4 0x27 0x0
|
|
0x03e0 0x0f 0x0
|
|
0x060c 0x1d 0x0
|
|
0x0614 0x07 0x0
|
|
0x0620 0xc1 0x0
|
|
0x0694 0x00 0x0
|
|
0x03d0 0x8c 0x0
|
|
0x0368 0x17 0x0
|
|
0x0200 0x00 0x0
|
|
0x0244 0x03 0x0>;
|
|
|
|
qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500
|
|
0x04d0 0x04d4 0x03c0 0x0630 0x0230
|
|
0x0000>;
|
|
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730
|
|
0x0734 0x0738 0x073c>;
|
|
qcom,phy-debug-reg = <0x01cc 0x01d0 0x01d4 0x01d8 0x01dc
|
|
0x01e0 0x01e4 0x01f8 0x0ed0 0x16d0
|
|
0x0edc 0x16dc 0x11e0 0x19e0 0x0a00
|
|
0x1200 0x0a04 0x1204 0x0a08 0x1208
|
|
0x0a0c 0x120c 0x0a10 0x1210 0x0a14
|
|
0x1214 0x0a18 0x1218 0x0c20 0x1420
|
|
0x0214 0x0218 0x021c 0x0220 0x0224
|
|
0x0228 0x022c 0x0230 0x0234 0x0238
|
|
0x023c 0x0600 0x0604>;
|
|
|
|
qcom,pcie-sm-branch-offset = <0x1000>;
|
|
qcom,pcie-sm-start-offset = <0x1090>;
|
|
|
|
qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
|
|
<0x28007003>, <0x80804002>, <0x70021c01>,
|
|
<0x18001802>, <0x70005000>, <0x10004000>,
|
|
<0x80814002>, <0x18001c01>, <0x1c018080>,
|
|
<0x0000100>;
|
|
|
|
qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
|
|
<0x0>, <0x0>;
|
|
|
|
qcom,pcie-sm-debug = <0x1040>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */
|
|
<0x1048>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */
|
|
<0x1050>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */
|
|
<0x1058>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */
|
|
<0x1060>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */
|
|
<0x1068>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */
|
|
<0x1070>, /* PCIE_SMs_SEQ_PWR_CTRL_STATUS */
|
|
<0x1078>, /* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */
|
|
<0x1080>, /* PCIE_SMs_SEQ_BR_EVENT_STATUS */
|
|
<0x1088>, /* PCIE_SMs_SEQ_PC_VAL */
|
|
<0x1090>, /* PCIE_SMs_SEQ_START */
|
|
<0x1094>, /* PCIE_SMs_CLKREQ_GATE */
|
|
<0x1098>, /* PCIE_SMs_CLKREQ_UNGATE */
|
|
<0x109C>; /* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */
|
|
|
|
pcie0_rp: pcie0_rp {
|
|
reg = <0 0 0 0 0>;
|
|
};
|
|
};
|
|
|
|
- |
|
|
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
|
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/clock/qcom,tcsrcc-pineapple.h>
|
|
pcie1: pcie@1c08000 {
|
|
compatible = "qcom,pci-msm";
|
|
device_type = "pci";
|
|
|
|
reg = <0x01c08000 0x3000>,
|
|
<0x01c0e000 0x2000>,
|
|
<0x40000000 0xf1d>,
|
|
<0x40000f20 0xa8>,
|
|
<0x40001000 0x1000>,
|
|
<0x40100000 0x100000>;
|
|
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
|
|
|
|
cell-index = <1>;
|
|
linux,pci-domain = <1>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
|
"int_d";
|
|
|
|
msi-map = <0x0 &gic_its 0x1480 0x1>,
|
|
<0x100 &gic_its 0x1481 0x1>; /* 32 event IDs */
|
|
|
|
perst-gpio = <&tlmm 97 0>;
|
|
wake-gpio = <&tlmm 99 0>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pcie1_perst_default
|
|
&pcie1_clkreq_default
|
|
&pcie1_wake_default>;
|
|
pinctrl-1 = <&pcie1_perst_default
|
|
&pcie1_clkreq_sleep
|
|
&pcie1_wake_default>;
|
|
|
|
gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
|
|
gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
|
|
vreg-1p2-supply = <&pm_v8_l3>;
|
|
vreg-0p9-supply = <&pm_v6e_l3>;
|
|
vreg-qref-supply = <&pm_v8_l1>;
|
|
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
|
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
|
|
|
qcom,vreg-1p2-voltage-level = <1200000 1200000 26100>;
|
|
qcom,vreg-0p9-voltage-level = <912000 880000 193000>;
|
|
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
|
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
|
qcom,vreg-qref-voltage-level = <880000 880000 25700>;
|
|
qcom,bw-scale = /* Gen1 */
|
|
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen2 */
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen3 */
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
100000000
|
|
/* Gen4 */
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
100000000>;
|
|
|
|
interconnect-names = "icc_path";
|
|
interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
|
|
|
|
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
|
<&tcsrcc TCSR_PCIE_1_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
|
|
<&pcie_1_pipe_clk>,
|
|
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
|
|
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
|
"pcie_aux_clk", "pcie_cfg_ahb_clk",
|
|
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
|
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
|
|
"pcie_rate_change_clk",
|
|
"gcc_ddrss_pcie_sf_qtb_clk",
|
|
"pcie_aggre_noc_axi_clk",
|
|
"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
|
|
"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
|
|
qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>,
|
|
<0>, <100000000>, <0>, <0>, <0>, <0>, <0>, <0>;
|
|
|
|
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
|
<0>, <0>, <0>, <1>, <0>, <0>, <0>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>,
|
|
<&gcc GCC_PCIE_1_PHY_BCR>,
|
|
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>,
|
|
<&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
|
|
reset-names = "pcie_1_core_reset",
|
|
"pcie_1_phy_reset",
|
|
"pcie_1_link_down_reset",
|
|
"pcie_1_phy_nocsr_com_phy_reset";
|
|
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1480>;
|
|
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
|
|
<0x100 &apps_smmu 0x1481 0x1>;
|
|
|
|
qcom,boot-option = <0x1>;
|
|
qcom,aux-clk-freq = <17>; /* 16.6 MHz */
|
|
qcom,drv-name = "lpass";
|
|
qcom,drv-l1ss-timeout-us = <5000>;
|
|
qcom,eq-fmdc-t-min-phase23 = <1>;
|
|
qcom,slv-addr-space-size = <0x20000000>;
|
|
qcom,ep-latency = <10>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
qcom,l1-2-th-scale = <2>;
|
|
qcom,l1-2-th-value = <150>;
|
|
|
|
qcom,pcie-clkreq-offset = <0x2c48>;
|
|
|
|
qcom,pcie-phy-ver = <106>;
|
|
qcom,phy-status-offset = <0x1214>;
|
|
qcom,phy-status-bit = <7>;
|
|
qcom,phy-power-down-offset = <0x1240>;
|
|
|
|
qcom,phy-sequence = <0x1240 0x03 0x0
|
|
0x0030 0x1d 0x0
|
|
0x0034 0x03 0x0
|
|
0x0078 0x01 0x0
|
|
0x007c 0x00 0x0
|
|
0x0080 0x51 0x0
|
|
0x00ac 0x34 0x0
|
|
0x0208 0x0c 0x0
|
|
0x020c 0x0a 0x0
|
|
0x0218 0x04 0x0
|
|
0x0220 0x16 0x0
|
|
0x0234 0x00 0x0
|
|
0x029c 0x80 0x0
|
|
0x02a0 0x7c 0x0
|
|
0x02b4 0x05 0x0
|
|
0x02e8 0x0a 0x0
|
|
0x030c 0x0d 0x0
|
|
0x0320 0x0b 0x0
|
|
0x0348 0x1c 0x0
|
|
0x0388 0x20 0x0
|
|
0x0394 0x30 0x0
|
|
0x03dc 0x09 0x0
|
|
0x03f4 0x14 0x0
|
|
0x03f8 0xb3 0x0
|
|
0x03fc 0x58 0x0
|
|
0x0400 0x9a 0x0
|
|
0x0404 0x26 0x0
|
|
0x0408 0xb6 0x0
|
|
0x040c 0xee 0x0
|
|
0x0410 0xdb 0x0
|
|
0x0414 0xdb 0x0
|
|
0x0418 0xa0 0x0
|
|
0x041c 0xdf 0x0
|
|
0x0420 0x78 0x0
|
|
0x0424 0x76 0x0
|
|
0x0428 0xff 0x0
|
|
0x0830 0x1d 0x0
|
|
0x0834 0x03 0x0
|
|
0x0878 0x01 0x0
|
|
0x087c 0x00 0x0
|
|
0x0880 0x51 0x0
|
|
0x08ac 0x34 0x0
|
|
0x0a08 0x0c 0x0
|
|
0x0a0c 0x0a 0x0
|
|
0x0a18 0x04 0x0
|
|
0x0a20 0x16 0x0
|
|
0x0a34 0x00 0x0
|
|
0x0a9c 0x80 0x0
|
|
0x0aa0 0x7c 0x0
|
|
0x0ab4 0x05 0x0
|
|
0x0ae8 0x0a 0x0
|
|
0x0b0c 0x0d 0x0
|
|
0x0b20 0x0b 0x0
|
|
0x0b48 0x1c 0x0
|
|
0x0b88 0x20 0x0
|
|
0x0b94 0x30 0x0
|
|
0x0bdc 0x09 0x0
|
|
0x0bf4 0x14 0x0
|
|
0x0bf8 0xb3 0x0
|
|
0x0bfc 0x58 0x0
|
|
0x0c00 0x9a 0x0
|
|
0x0c04 0x26 0x0
|
|
0x0c08 0xb6 0x0
|
|
0x0c0c 0xee 0x0
|
|
0x0c10 0xdb 0x0
|
|
0x0c14 0xdb 0x0
|
|
0x0c18 0xa0 0x0
|
|
0x0c1c 0xdf 0x0
|
|
0x0c20 0x78 0x0
|
|
0x0c24 0x76 0x0
|
|
0x0c28 0xff 0x0
|
|
0x0ea0 0x01 0x0
|
|
0x0eb4 0x00 0x0
|
|
0x0ec4 0x00 0x0
|
|
0x0ec8 0x1f 0x0
|
|
0x0ed4 0x12 0x0
|
|
0x0ed8 0x12 0x0
|
|
0x0edc 0xdb 0x0
|
|
0x0ee0 0x9a 0x0
|
|
0x0ee4 0x38 0x0
|
|
0x0ee8 0xb6 0x0
|
|
0x0eec 0x64 0x0
|
|
0x0ef0 0x1f 0x0
|
|
0x0ef4 0x1f 0x0
|
|
0x0ef8 0x1f 0x0
|
|
0x0efc 0x1f 0x0
|
|
0x0f00 0x1f 0x0
|
|
0x0f04 0x1f 0x0
|
|
0x0f0c 0x1f 0x0
|
|
0x0f14 0x1f 0x0
|
|
0x0f1c 0x1f 0x0
|
|
0x0f28 0x5b 0x0
|
|
0x1000 0x26 0x0
|
|
0x1004 0x03 0x0
|
|
0x1010 0x06 0x0
|
|
0x1014 0x16 0x0
|
|
0x1018 0x36 0x0
|
|
0x101c 0x04 0x0
|
|
0x1020 0x0a 0x0
|
|
0x1024 0x1a 0x0
|
|
0x1028 0x68 0x0
|
|
0x1030 0xab 0x0
|
|
0x1034 0xaa 0x0
|
|
0x1038 0x02 0x0
|
|
0x103c 0x12 0x0
|
|
0x1060 0xf8 0x0
|
|
0x1064 0x01 0x0
|
|
0x1070 0x06 0x0
|
|
0x1074 0x16 0x0
|
|
0x1078 0x36 0x0
|
|
0x107c 0x0a 0x0
|
|
0x1080 0x04 0x0
|
|
0x1084 0x0d 0x0
|
|
0x1088 0x41 0x0
|
|
0x1090 0xab 0x0
|
|
0x1094 0xaa 0x0
|
|
0x1098 0x01 0x0
|
|
0x109c 0x00 0x0
|
|
0x10bc 0x0a 0x0
|
|
0x10c0 0x01 0x0
|
|
0x10cc 0x62 0x0
|
|
0x10d0 0x02 0x0
|
|
0x10d8 0x40 0x0
|
|
0x10dc 0x14 0x0
|
|
0x10e0 0x90 0x0
|
|
0x10e4 0x82 0x0
|
|
0x10f4 0x0f 0x0
|
|
0x1110 0x08 0x0
|
|
0x1120 0x46 0x0
|
|
0x1124 0x04 0x0
|
|
0x1140 0x14 0x0
|
|
0x1164 0x34 0x0
|
|
0x1170 0xa0 0x0
|
|
0x1174 0x06 0x0
|
|
0x1184 0x88 0x0
|
|
0x1188 0x14 0x0
|
|
0x1198 0x0f 0x0
|
|
0x129c 0x87 0x0
|
|
0x12a0 0x05 0x0
|
|
0x12a4 0xa1 0x0
|
|
0x1378 0x2e 0x0
|
|
0x1390 0xcc 0x0
|
|
0x13f8 0x00 0x0
|
|
0x13fc 0x22 0x0
|
|
0x141c 0xc1 0x0
|
|
0x1450 0x0f 0x0
|
|
0x1490 0x00 0x0
|
|
0x14a0 0x16 0x0
|
|
0x14f0 0x27 0x0
|
|
0x14f4 0x27 0x0
|
|
0x1508 0x02 0x0
|
|
0x155c 0x2e 0x0
|
|
0x157c 0x03 0x0
|
|
0x1584 0x28 0x0
|
|
0x13dc 0x04 0x0
|
|
0x13e0 0x02 0x0
|
|
0x1418 0xc0 0x0
|
|
0x140c 0x1d 0x0
|
|
0x158c 0x0f 0x0
|
|
0x15ac 0xf2 0x0
|
|
0x15c0 0xf2 0x0
|
|
0x1370 0x17 0x0
|
|
0x1200 0x00 0x0
|
|
0x1244 0x03 0x0>;
|
|
|
|
qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500
|
|
0x04d0 0x04d4 0x03c0 0x0630 0x0230
|
|
0x0000>;
|
|
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730
|
|
0x0734 0x0738 0x073c>;
|
|
qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc
|
|
0x11e0 0x11e4 0x11f8 0x00b8 0x08b8
|
|
0x00c4 0x08c4 0x0464 0x0c64 0x1800
|
|
0x1c00 0x1804 0x1c04 0x1808 0x1c08
|
|
0x180c 0x1c0c 0x1810 0x1c10 0x1814
|
|
0x1c14 0x1818 0x1c18 0x1a20 0x1e20
|
|
0x1214 0x1218 0x121c 0x1220 0x1224
|
|
0x1228 0x122c 0x1230 0x1234 0x1238
|
|
0x123c 0x1400 0x1404>;
|
|
|
|
pcie1_rp: pcie1_rp {
|
|
reg = <0 0 0 0 0>;
|
|
};
|
|
};
|