6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
53 lines
1.4 KiB
Plaintext
53 lines
1.4 KiB
Plaintext
NXP LPC32xx SoC NAND SLC controller
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Required properties:
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- compatible: "nxp,lpc3220-slc"
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- reg: Address and size of the controller
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- nand-on-flash-bbt: Use bad block table on flash
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- gpios: GPIO specification for NAND write protect
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The following required properties are very controller specific. See the LPC32xx
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User Manual:
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- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
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- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
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(The following values are specified in Hz, to make them independent of actual
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clock speed:)
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- nxp,wwidth: Write pulse width (W_WIDTH)
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- nxp,whold: Write hold time (W_HOLD)
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- nxp,wsetup: Write setup time (W_SETUP)
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- nxp,rwidth: Read pulse width (R_WIDTH)
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- nxp,rhold: Read hold time (R_HOLD)
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- nxp,rsetup: Read setup time (R_SETUP)
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Optional subnodes:
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- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
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Example:
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slc: flash@20020000 {
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compatible = "nxp,lpc3220-slc";
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reg = <0x20020000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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nxp,wdr-clks = <14>;
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nxp,wwidth = <40000000>;
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nxp,whold = <100000000>;
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nxp,wsetup = <100000000>;
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nxp,rdr-clks = <14>;
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nxp,rwidth = <40000000>;
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nxp,rhold = <66666666>;
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nxp,rsetup = <100000000>;
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nand-on-flash-bbt;
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gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
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mtd0@00000000 {
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label = "phy3250-boot";
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reg = <0x00000000 0x00064000>;
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read-only;
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};
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...
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};
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