6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
161 lines
4.1 KiB
YAML
161 lines
4.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Ocelot Externally-Controlled Ethernet Switch
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maintainers:
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- Colin Foster <colin.foster@in-advantage.com>
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description: |
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The Ocelot ethernet switch family contains chips that have an internal CPU
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(VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
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the option to be controlled externally, which is the purpose of this driver.
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The switch family is a multi-port networking switch that supports many
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interfaces. Additionally, the device can perform pin control, MDIO buses, and
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external GPIO expanders.
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properties:
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compatible:
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enum:
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- mscc,vsc7512
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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spi-max-frequency:
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maxItems: 1
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patternProperties:
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"^pinctrl@[0-9a-f]+$":
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type: object
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$ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
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"^gpio@[0-9a-f]+$":
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type: object
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$ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
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properties:
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compatible:
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enum:
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- mscc,ocelot-sgpio
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"^mdio@[0-9a-f]+$":
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type: object
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$ref: /schemas/net/mscc,miim.yaml
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properties:
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compatible:
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enum:
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- mscc,ocelot-miim
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required:
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- compatible
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- reg
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- '#address-cells'
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- '#size-cells'
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- spi-max-frequency
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additionalProperties: false
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examples:
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- |
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ocelot_clock: ocelot-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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soc@0 {
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compatible = "mscc,vsc7512";
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spi-max-frequency = <2500000>;
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mdio@7107009c {
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compatible = "mscc,ocelot-miim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7107009c 0x24>;
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sw_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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mdio@710700c0 {
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compatible = "mscc,ocelot-miim";
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pinctrl-names = "default";
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pinctrl-0 = <&miim1_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x710700c0 0x24>;
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sw_phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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};
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gpio: pinctrl@71070034 {
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compatible = "mscc,ocelot-pinctrl";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 22>;
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reg = <0x71070034 0x6c>;
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sgpio_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
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function = "sg0";
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};
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miim1_pins: miim1-pins {
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pins = "GPIO_14", "GPIO_15";
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function = "miim";
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};
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};
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gpio@710700f8 {
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compatible = "mscc,ocelot-sgpio";
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#address-cells = <1>;
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#size-cells = <0>;
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bus-frequency = <12500000>;
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clocks = <&ocelot_clock>;
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microchip,sgpio-port-ranges = <0 15>;
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pinctrl-names = "default";
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pinctrl-0 = <&sgpio_pins>;
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reg = <0x710700f8 0x100>;
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sgpio_in0: gpio@0 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <64>;
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};
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sgpio_out1: gpio@1 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <64>;
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};
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};
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};
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};
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...
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