6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
44 lines
1.6 KiB
Plaintext
44 lines
1.6 KiB
Plaintext
Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
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Synopsys DesignWare provides interrupt controller IP for APB known as
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dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
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APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
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controller in some SoCs, e.g. Hisilicon SD5203.
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Required properties:
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- compatible: shall be "snps,dw-apb-ictl"
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- reg: physical base address of the controller and length of memory mapped
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region starting with ENABLE_LOW register
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
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Additional required property when it's used as secondary interrupt controller:
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- interrupts: interrupt reference to primary interrupt controller
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The interrupt sources map to the corresponding bits in the interrupt
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registers, i.e.
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- 0 maps to bit 0 of low interrupts,
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- 1 maps to bit 1 of low interrupts,
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- 32 maps to bit 0 of high interrupts,
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- 33 maps to bit 1 of high interrupts,
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- (optional) fast interrupts start at 64.
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Example:
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/* dw_apb_ictl is used as secondary interrupt controller */
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aic: interrupt-controller@3000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x3000 0xc00>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* dw_apb_ictl is used as primary interrupt controller */
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vic: interrupt-controller@10130000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x10130000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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