6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
88 lines
2.0 KiB
YAML
88 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Realtek RTL SoC interrupt controller devicetree bindings
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description:
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Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
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interrupt to be routed to one parent CPU (hardware) interrupt, or left
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disconnected.
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All connected input lines from SoC peripherals can be masked individually,
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and an interrupt status register is present to indicate which interrupts are
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pending.
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maintainers:
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- Birger Koblitz <mail@birger-koblitz.de>
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- Bert Vermeulen <bert@biot.com>
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- John Crispin <john@phrozen.org>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- realtek,rtl8380-intc
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- const: realtek,rtl-intc
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- const: realtek,rtl-intc
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deprecated: true
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"#interrupt-cells":
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description:
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SoC interrupt line index.
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const: 1
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 15
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description:
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List of parent interrupts, in the order that they are connected to this
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interrupt router's outputs, starting at the first output.
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interrupt-controller: true
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interrupt-map:
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deprecated: true
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description: Describes mapping from SoC interrupts to CPU interrupts
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required:
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- compatible
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- reg
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- "#interrupt-cells"
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- interrupt-controller
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allOf:
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- if:
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properties:
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compatible:
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const: realtek,rtl-intc
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then:
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properties:
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"#address-cells":
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const: 0
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required:
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- "#address-cells"
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- interrupt-map
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else:
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required:
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- interrupts
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additionalProperties: false
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examples:
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- |
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interrupt-controller@3000 {
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compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0x3000 0x18>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>, <3>, <4>, <5>, <6>;
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};
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