2e6858f742
Add i3c msm geni driver binding for Sun device. Change-Id: I3bb5c66bd182fe8d527c72c95aa88ee746ce4127 Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
109 lines
2.4 KiB
YAML
109 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i3c/qcom,i3c-master-msm-geni.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies Inc.'s GENI based I3C controller
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maintainers:
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- Mukesh Savaliya <quic_msavaliy@quicinc.com>
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description:
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I3C busses can be described with a node for the primary I3C controller device
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and a set of child nodes for each I2C or I3C slave on the bus. Each of them
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may, during the life of the bus, request mastership.
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allOf:
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- $ref: i3c.yaml#
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properties:
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compatible:
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const: qcom,geni-i3c
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clocks:
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maxItems: 1
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clock-names:
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const: se-clk
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pinctrl-0: true
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pinctrl-1: true
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interconnects:
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minItems: 2
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maxItems: 3
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interconnect-names:
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minItems: 2
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items:
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- const: qup-core
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- const: qup-config
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- const: qup-memory
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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qcom,ibi-ctrl-id:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- pinctrl-names
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- qcom,ibi-ctrl-id
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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i3c0: i3c-master@a80000 {
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compatible = "qcom,geni-i3c";
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reg = <0xa80000 0x4000>,
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<0xec90000 0x10000>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep", "disable";
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pinctrl-0 = <&qupv3_se0_i3c_sda_active>, <&qupv3_se0_i3c_scl_active>;
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pinctrl-1 = <&qupv3_se0_i3c_sda_sleep>, <&qupv3_se0_i3c_scl_sleep>;
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pinctrl-2 = <&qupv3_se0_i3c_disable>;
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interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 31 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <3>;
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#size-cells = <0>;
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qcom,ibi-ctrl-id = <0>;
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};
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...
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