7f491b9af4
Add gpi driver binding for Sun device. Change-Id: I6667f73eb4258b107eb0a5060efeffd55a9075a6 Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
117 lines
2.9 KiB
YAML
117 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/qcom,msm_gpi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies Inc GPI DMA controller
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maintainers:
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- Mukesh Savaliya <quic_msavaliy@quicinc.com>
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description: |
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QCOM GPI DMA controller provides DMA capabilities for
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peripheral buses such as I2C, UART, and SPI.
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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compatible:
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enum:
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- qcom,gpi-dma
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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interrupts:
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description:
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Interrupt lines for each GPI instance
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minItems: 1
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maxItems: 12
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"#dma-cells":
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const: 3
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description: >
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DMA clients must use the format described in dma.txt, giving a phandle
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to the DMA controller plus the following 3 integer cells:
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- channel: if set to 0xffffffff, any available channel will be allocated
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for the client. Otherwise, the exact channel specified will be used.
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- seid: serial id of the client as defined in the SoC documentation.
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- client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
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iommus:
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maxItems: 1
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qcom,max-num-gpii:
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maximum: 12
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qcom,gpii-mask:
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maxItems: 1
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qcom,static-gpii-mask:
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maxItems: 1
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qcom,ev-factor:
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maxItems: 1
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qcom,qcom,iommu-dma-addr-pool:
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maxItems: 1
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qcom,gpi-ee-offset:
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maxItems: 1
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dma-coherent:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- dma-cells
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- iommus
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- qcom,max-num-gpii
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- qcom,gpii-mask
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- qcom,ev-factor
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- qcom,qcom,iommu-dma-addr-pool
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- gpi-ee-offset
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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gpi_dma1: qcom,gpi-dma@a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0xb6 0x0>;
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qcom,max-num-gpii = <12>;
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interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,static-gpii-mask = <0x3>;
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qcom,gpii-mask = <0xc>;
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qcom,ev-factor = <1>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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dma-coherent;
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};
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...
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