6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
59 lines
1.8 KiB
Plaintext
59 lines
1.8 KiB
Plaintext
* Rockchip RK3328 Clock and Reset Unit
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The RK3328 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3328-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing pll rates are not changeable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "clkin_i2s" - external I2S clock - optional,
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- "gmac_clkin" - external GMAC clock - optional
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- "phy_50m_out" - output clock of the pll in the mac phy
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- "hdmi_phy" - output clock of the hdmi phy pll - optional
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Example: Clock controller node:
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cru: clock-controller@ff440000 {
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compatible = "rockchip,rk3328-cru";
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reg = <0x0 0xff440000 0x0 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@ff120000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff120000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART0>;
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};
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