6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
60 lines
1.2 KiB
Plaintext
60 lines
1.2 KiB
Plaintext
Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
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clkdiv configures the clock frequency of a set of outputs on the PMIC.
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These clocks are typically wired through alternate functions on
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gpio pins.
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=======================
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Properties
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=======================
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be "qcom,spmi-clkdiv".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: base address of CLKDIV peripherals.
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- qcom,num-clkdivs
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Usage: required
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Value type: <u32>
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Definition: number of CLKDIV peripherals.
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the xo clock.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "xo".
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- #clock-cells:
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Usage: required
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Value type: <u32>
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Definition: shall contain 1.
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=======
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Example
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=======
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pm8998_clk_divs: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <3>;
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clocks = <&xo_board>;
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clock-names = "xo";
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assigned-clocks = <&pm8998_clk_divs 1>,
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<&pm8998_clk_divs 2>,
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<&pm8998_clk_divs 3>;
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assigned-clock-rates = <9600000>,
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<9600000>,
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<9600000>;
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};
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