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android_kernel_samsung_sm87…/bindings/clock/qcom,gcc-pineapple.yaml
Xubin Bai b6870400ed dt-bindings: clock: Add GCC clock controller bindings for Pineapple
Add GCC clock controller binding for Pineapple device.

Change-Id: I9be4c727fe47bf6c7551c5c23fd02a61bd25fb8c
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
2023-06-12 21:18:40 -07:00

104 lines
3.0 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-pineapple.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller Binding for Pineapple
maintainers:
- Xubin Bai <quic_xubibai@quicinc.com>
description: |
Global clock control module which supports the clocks, resets and
power domains on Pineapple
See also:
- dt-bindings/clock/qcom,gcc-pineapple.h
properties:
compatible:
const: qcom,pineapple-gcc
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: PCIE 0 Pipe clock source (Optional clock)
- description: PCIE 1 Phy_aux clock source (Optional clock)
- description: PCIE 1 pipe clock source (Optional clock)
- description: Sleep clock source
- description: UFS Phy Rx symbol 0 clock source (Optional clock)
- description: UFS Phy Rx symbol 1 clock source (Optional clock)
- description: UFS Phy Tx symbol 0 clock source (Optional clock)
- description: USB3 Phy wrapper pipe clock source (Optional clock)
minItems: 2
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: pcie_0_pipe_clk # Optional clock
- const: pcie_1_phy_aux_clk # Optional clock
- const: pcie_1_pipe_clk # Optional clock
- const: sleep_clk
- const: ufs_phy_rx_symbol_0_clk # Optional clock
- const: ufs_phy_rx_symbol_1_clk # Optional clock
- const: ufs_phy_tx_symbol_0_clk # Optional clock
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
minItems: 2
vdd_cx-supply:
description: Phandle pointer to the vdd_cx logic rail supply
vdd_mxa-supply:
description: Phandle pointer to the vdd_mxa logic rail supply
vdd_cx_ao-supply:
description: Phandle pointer to the vdd_cx_ao logic rail supply
required:
- compatible
- clocks
- clock-names
allOf:
- $ref: "qcom,gcc.yaml#"
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,pineapple-gcc", "syscon";
reg = <0x100000 0x1f4200>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&pcie_0_pipe_clk>,
<&pcie_1_phy_aux_clk>,
<&pcie_1_pipe_clk>,
<&sleep_clk>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"pcie_0_pipe_clk",
"pcie_1_phy_aux_clk",
"pcie_1_pipe_clk",
"sleep_clk",
"ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
...