24e6ec54d7
Add clock controller bindings for GCC/GPUCC/DISPCC/DEBUGCC on Monaco Platform. Add clock controller bindings for RPMCC for Monaco, Khaje and Holi platform. Change-Id: I98e6b2094daabc6e6b8b450a397ea3c19799b50a Signed-off-by: Prerna Singh <quic_prersing@quicinc.com>
76 lines
1.9 KiB
YAML
76 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-monaco.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Display Clock & Reset Controller
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm Technologies, Inc. display clock control module which supports the clocks and
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power domains on Monaco.
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See also:
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dt-bindings/clock/qcom,dispcc-monaco.h
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properties:
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compatible:
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enum:
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- qcom,monaco-dispcc
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clocks:
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items:
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- description: Brard XO source
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- description: Brard XO_AO source
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- description: Sleep clock source
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- description: GPLL0 OUT MAIN clock source
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- const: gpll0_out_main
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vdd_cx-supply:
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description: Phandle pointer to the vdd_cx logic rail supply
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vdd_mxa-supply:
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description: Phandle pointer to the vdd_mxa logic rail supply
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'#clock-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-monaco.h>
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dispcc: clock-controller@5f00000 {
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compatible = "qcom,monaco-dispcc", "syscon";
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reg = <0x05f00000 0x20000>;
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reg-names = "cc_base";
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clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
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"sleep_clk";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
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<&gcc GPLL0>, <&sleep_clk>;
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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