6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
34 lines
869 B
Plaintext
34 lines
869 B
Plaintext
Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
|
|
|
|
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
|
|
|
|
Required Properties:
|
|
- compatible: has to be "qca,<soctype>-pll" and one of the following
|
|
fallbacks:
|
|
- "qca,ar7100-pll"
|
|
- "qca,ar7240-pll"
|
|
- "qca,ar9130-pll"
|
|
- "qca,ar9330-pll"
|
|
- "qca,ar9340-pll"
|
|
- "qca,qca9550-pll"
|
|
- reg: Base address and size of the controllers memory area
|
|
- clock-names: Name of the input clock, has to be "ref"
|
|
- clocks: phandle of the external reference clock
|
|
- #clock-cells: has to be one
|
|
|
|
Optional properties:
|
|
- clock-output-names: should be "cpu", "ddr", "ahb"
|
|
|
|
Example:
|
|
|
|
pll-controller@18050000 {
|
|
compatible = "qca,ar9132-pll", "qca,ar9130-pll";
|
|
reg = <0x18050000 0x20>;
|
|
|
|
clock-names = "ref";
|
|
clocks = <&extosc>;
|
|
|
|
#clock-cells = <1>;
|
|
clock-output-names = "cpu", "ddr", "ahb";
|
|
};
|