6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
56 lines
1.3 KiB
YAML
56 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Freescale SAI bitclock-as-a-clock binding
|
|
|
|
maintainers:
|
|
- Michael Walle <michael@walle.cc>
|
|
|
|
description: |
|
|
It is possible to use the BCLK pin of a SAI module as a generic clock
|
|
output. Some SoC are very constrained in their pin multiplexer
|
|
configuration. Eg. pins can only be changed groups. For example, on the
|
|
LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
|
|
the second pins are wasted. Using this binding it is possible to use the
|
|
clock of the second SAI as a MCLK clock for an audio codec, for example.
|
|
|
|
This is a composite of a gated clock and a divider clock.
|
|
|
|
properties:
|
|
compatible:
|
|
const: fsl,vf610-sai-clock
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
'#clock-cells':
|
|
const: 0
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- '#clock-cells'
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
mclk: clock-mclk@f130080 {
|
|
compatible = "fsl,vf610-sai-clock";
|
|
reg = <0x0 0xf130080 0x0 0x80>;
|
|
#clock-cells = <0>;
|
|
clocks = <&parentclk>;
|
|
};
|
|
};
|