// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,evacc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include <dt-bindings/clock/qcom,gpucc-tuna.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-tuna.h>
#include <dt-bindings/interconnect/qcom,tuna.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/clock/qcom,aop-qmp.h>

/ {
	model = "Qualcomm Technologies, Inc. Tuna";
	compatible = "qcom,tuna";
	qcom,msm-id = <655 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	memory {
		device_type = "memory";
		reg = <0 0 0 0>;
	};

	aliases: aliases {
		serial0 = &qupv3_se7_2uart;
		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
		mmc1 = &sdhc_2; /* SDC2 SD card slot */
		hsuart0 = &qupv3_se14_4uart;
		i2c0 = &qupv3_se0_i2c;
		i2c1 = &qupv3_se1_i2c;
		i2c2 = &qupv3_se2_i2c;
		i2c3 = &qupv3_se3_i2c;
		i2c4 = &qupv3_se4_i2c;
		i2c5 = &qupv3_se5_i2c;
		i2c6 = &qupv3_se6_i2c;
		i2c8 = &qupv3_se8_i2c;
		i2c9 = &qupv3_se9_i2c;
		i2c10 = &qupv3_se10_i2c;
		i2c11 = &qupv3_se11_i2c;
		i2c12 = &qupv3_se12_i2c;
		i2c13 = &qupv3_se13_i2c;
		i2c15 = &qupv3_se15_i2c;
		spi0 = &qupv3_se0_spi;
		spi1 = &qupv3_se1_spi;
		spi2 = &qupv3_se2_spi;
		spi4 = &qupv3_se4_spi;
		spi5 = &qupv3_se5_spi;
		spi6 = &qupv3_se6_spi;
		spi8 = &qupv3_se8_spi;
		spi10 = &qupv3_se10_spi;
		spi11 = &qupv3_se11_spi;
		spi12 = &qupv3_se12_spi;
		spi13 = &qupv3_se13_spi;
		spi15 = &qupv3_se15_spi;
	};

	chosen: chosen {
		bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket";
		stdout-path = "serial0:115200n8";
	};

	reserved_memory: reserved-memory {};

	ddr-regions { };

	mem-offline {
		compatible = "qcom,mem-offline";
		offline-sizes = <0x2 0xc0000000 0x1 0x0>;
		granule = <512>;
		qcom,qmp = <&aoss_qmp>;
		status = "disabled";
	};

	firmware: firmware {
		qcom_scm: qcom_scm {};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			L2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_1>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			L2_1: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 3>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_2>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <121>;
			L2_2: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 3>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_3>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <121>;
			L2_3: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 3>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_4>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <121>;
			L2_4: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_5>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <121>;
			L2_5: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_6>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <121>;
			L2_6: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 2>;
			#cooling-cells = <2>;
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_7>;
			capacity-dmips-mhz = <1157>;
			dynamic-power-coefficient = <295>;
			L2_7: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};

				core2 {
					cpu = <&CPU4>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU5>;
				};

				core1 {
					cpu = <&CPU6>;
				};
			};

			cluster3 {
				core0 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	idle-states {
		entry-method = "psci";

		GOLD_OFF_CL0: gold-cluster0-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <400>;
			exit-latency-us = <1100>;
			min-residency-us = <4011>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF_CL0: gold-cluster0-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <550>;
			exit-latency-us = <1050>;
			min-residency-us = <7951>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_OFF_CL1: gold-cluster1-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <400>;
			exit-latency-us = <1100>;
			min-residency-us = <4011>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF_CL1: gold-cluster1-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <550>;
			exit-latency-us = <1050>;
			min-residency-us = <7951>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_OFF_CL2: gold-cluster2-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <400>;
			exit-latency-us = <1100>;
			min-residency-us = <4011>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF_CL2: gold-cluster2-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <550>;
			exit-latency-us = <1050>;
			min-residency-us = <7951>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_PLUS_OFF: gold-plus-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <450>;
			exit-latency-us = <1200>;
			min-residency-us = <6230>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_PLUS_RAIL_OFF: gold-plus-cluster3-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <500>;
			exit-latency-us = <1350>;
			min-residency-us = <7480>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		CLUSTER_PWR_DN: cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			idle-state-name = "l3-off";
			entry-latency-us = <750>;
			exit-latency-us = <2350>;
			min-residency-us = <9144>;
			arm,psci-suspend-param = <0x41000044>;
		};

		CX_RET: cx-ret { /* Cx Ret */
			compatible = "domain-idle-state";
			idle-state-name = "cx-ret";
			entry-latency-us = <1561>;
			exit-latency-us = <2801>;
			min-residency-us = <8550>;
			arm,psci-suspend-param = <0x41001344>;
		};

		APSS_OFF: cluster-e3 { /* E3 */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <2800>;
			exit-latency-us = <4400>;
			min-residency-us = <10150>;
			arm,psci-suspend-param = <0x4100b344>;
		};
	};

	soc: soc { };

	hypervisor: hypervisor {
		gh_watchdog: qcom,gh-watchdog { };
	};
};

#include "tuna-reserved-memory.dtsi"
#include "msm-arm-smmu-tuna.dtsi"
#include "tuna-dma-heaps.dtsi"
#include "tuna-pcie.dtsi"

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	cdsp_eva_mem: cdsp_eva_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x400000>;
	};

	/* global autoconfigured region for contiguous allocations */
	system_cma: linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
		linux,cma-default;
	};

	kinfo_mem: debug_kinfo_region {
		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
		size = <0x0 0x1000>;
		no-map;
	};

	va_md_mem: va_md_mem_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		size = <0 0x1000000>;
	};

	ramoops_mem: ramoops-region {
		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
		size = <0x0 0x200000>;
		no-map;
	};
};

&firmware {
	qcom_scm {
		compatible = "qcom,scm";
		qcom,dload-mode = <&tcsr 0x19000>;
	};

	qcom_smcinvoke {
		compatible = "qcom,smcinvoke";
	};

	qcom_mem_object {
		compatible = "qcom,mem-object";
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD4: cpu-pd4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD5: cpu-pd5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD6: cpu-pd6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD7: cpu-pd7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: cluster-pd {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>;
		};
	};

	msm_gpu: qcom,kgsl-3d0@3d00000 { };

	intc: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		ranges;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,	/* GICD */
		      <0x17180000 0x200000>;	/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;
		#size-cells = <1>;
		gic_its: msi-controller@0x17140000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x17140000 0x20000>;
		};
	};

	qcom,hdcp {
		compatible = "qcom,hdcp";
		qcom,use-smcinvoke = <1>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
			      <0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};

	llcc: cache-controller@24800000 {
		compatible = "qcom,tuna-llcc";
		reg = <0x24800000 0x200000>, <0x25800000 0x200000>,
			<0x24C00000 0x200000>, <0x25C00000 0x200000>,
			<0x26800000 0x200000>, <0x26C00000 0x200000>;

		reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
				"llcc3_base", "llcc_broadcast_or_base",
				"llcc_broadcast_and_base";

		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		cap-based-alloc-and-pwr-collapse;

		llcc_perfmon {
			compatible = "qcom,llcc-perfmon";
			clocks = <&aoss_qmp QDSS_CLK>;
			clock-names = "qdss_clk";
		};
	};

	gic-interrupt-router {
		compatible = "qcom,gic-intr-routing";
		qcom,gic-class0-cpus = <&CPU0 &CPU1>;
		qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
	};

	apps_rsc: rsc@17a00000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x17a00000 0x10000>,
		      <0x17a10000 0x10000>,
		      <0x17a20000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		qcom,drv-count = <3>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&CLUSTER_PD>;

		apps_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0xd00>;
			qcom,tcs-distance = <0x2a0>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    3>,
						  <SLEEP_TCS     2>,
						  <WAKE_TCS      2>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 1>;
			};

			apps_bcm_voter: bcm_voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: clock-controller {
				compatible = "qcom,tuna-rpmh-clk";
				#clock-cells = <1>;
			};

			dcvs_fp: qcom,dcvs-fp {
				compatible = "qcom,dcvs-fp";
				qcom,ddr-bcm-name = "MC4";
				qcom,llcc-bcm-name = "SH5";
			};
		};
	};

	cluster-device {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD>;
	};

	qcom,secure-buffer {
		compatible = "qcom,secure-buffer";
		qcom,vmid-cp-camera-preview-ro;
	};

	qcom,mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "supplier";
		qcom,vmid = <3>;
	};

	qcom,mem-buf-msgq {
	       compatible = "qcom,mem-buf-msgq";
	       qcom,msgq-names = "trusted_vm", "oem_vm";
	};

	cam_rsc: rsc@adc8000 {
		label = "cam_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xadc8000 0x1000>,
		      <0xadc9000 0x1000>,
		      <0xadca000 0x1000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		qcom,drv-count = <3>;
		qcom,hw-channel;
		interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&camcc CAM_CC_DRV_AHB_CLK>;

		cam_rsc_drv0: drv@0 {
			qcom,drv-id = <0>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			channel@1 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			cam_bcm_voter0: bcm_voter {
				compatible = "qcom,bcm-voter";
				qcom,no-amc;
			};
		};

		cam_rsc_drv1: drv@1 {
			qcom,drv-id = <1>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			channel@1 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			cam_bcm_voter1: bcm_voter {
				compatible = "qcom,bcm-voter";
				qcom,no-amc;
			};
		};

		cam_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			channel@1 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			cam_bcm_voter2: bcm_voter {
				compatible = "qcom,bcm-voter";
				qcom,no-amc;
			};
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x1000>;
		reg-names = "drv-0";
		qcom,drv-count = <1>;
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;

		disp_rsc_drv0: drv@0 {
			qcom,drv-id = <0>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <SLEEP_TCS     1>,
						  <WAKE_TCS      1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};
	};

	disp_crm: crm@af21000 {
		label = "disp_crm";
		compatible = "qcom,disp-crm-v2";
		reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27400 0x400>,
		      <0xaf27800 0x2000>, <0xaf29800 0x700>, <0xaf29f00 0x100>;
		reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common";
		interrupts = <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 707 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "disp_crm_drv0",
				  "disp_crm_drv1",
				  "disp_crm_drv2",
				  "disp_crm_drv3",
				  "disp_crm_drv4",
				  "disp_crm_drv5";
		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
		qcom,hw-drv-ids = <0 1 2 3 4 5>;
		qcom,sw-drv-ids = <0 1 2 3 4 5>;
	};

	cam_crm: crm@adcb000 {
		label = "cam_crm";
		compatible = "qcom,cam-crm-v2";
		reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd200 0x400>,
		      <0xadcd600 0x2000>, <0xadcf600 0x700>, <0xadcfd00 0x100>;
		reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common";
		interrupts = <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "cam_crm_drv0";
		clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
		qcom,hw-drv-ids = <0 1 2>;
		qcom,sw-drv-ids = <0>;
	};

	pcie_crm: crm@1d01000 {
		label = "pcie_crm";
		compatible = "qcom,pcie-crm-v2";
		reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03400 0x400>,
		      <0x1d03800 0x2000>, <0x1d05800 0x700>, <0x1d05f00 0x100>;
		reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common";
		interrupts = <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "pcie_crm_drv0";
		clocks = <&pcie_0_pipe_clk>;
		qcom,hw-drv-ids = <0 1>;
		qcom,sw-drv-ids = <0>;
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,tuna-pdc", "qcom,pdc";
		reg = <0xb220000 0x10000>, <0x174000f0 0x64>;
		qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
				  <10 230 1>, <11 724 1>, <12 716 1>,
				  <13 727 1>, <14 720 1>, <15 726 1>,
				  <16 721 1>, <17 262 1>, <18 70 1>,
				  <19 723 1>, <20 234 1>, <22 725 1>,
				  <23 231 1>, <24 504 14>, <40 520 6>,
				  <51 531 4>, <58 538 2>, <61 541 4>,
				  <67 547 27>, <94 609 31>, <125 63 1>,
				  <126 366 2>, <128 374 1>, <129 378 1>,
				  <130 428 1>, <131 434 2>, <133 437 1>,
				  <134 452 2>, <136 458 2>, <138 464 11>,
				  <149 671 1>, <150 688 1>, <151 714 2>,
				  <153 722 1>, <154 255 1>, <155 269 2>,
				  <157 276 1>, <158 287 1>, <159 306 4>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	adsp_sleepmon: adsp-sleepmon {
		compatible = "qcom,adsp-sleepmon";
		qcom,rproc-handle = <&adsp_pas>;
	};

	pcie_pdc: pdc@b360000 {
		compatible = "qcom,tuna-pcie-pdc", "qcom,pcie-pdc";
		reg = <0xb360000 0x10000>;
	};

	adsp_pas: remoteproc-adsp@03000000 {
		compatible = "qcom,tuna-adsp-pas";
		reg = <0x03000000 0x10000>;
		status = "ok";

		cx-supply = <&VDD_LPI_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		mx-supply = <&VDD_LPI_MX_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		reg-names = "cx", "mx";
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>,
				<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "rproc_ddr", "crypto_ddr";

		firmware-name = "adsp.mdt", "adsp_dtb.mdt";
		memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>;
		/* Inputs from ssc */
		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					<&adsp_smp2p_in 0 0>,
					<&adsp_smp2p_in 2 0>,
					<&adsp_smp2p_in 1 0>,
					<&adsp_smp2p_in 3 0>,
					<&adsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to turing */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		remoteproc_adsp_glink: glink-edge {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "adsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_LPASS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,net-id = <2>;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;

				qcom,no-wake-svc = <0x190>;
			};

			qcom,pmic_glink_rpmsg {
				qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
			};

			qcom,pmic_glink_log_rpmsg {
				qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
				qcom,intents = <0x800 5
						0xc00 3
						0x2000 1>;
			};
		};
	};

	cdsp_pas: remoteproc-cdsp@32300000 {
		compatible = "qcom,tuna-cdsp-pas";
		reg = <0x32300000 0x10000>;
		status = "ok";

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-supply = <&VDD_MXC_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		nsp-supply = <&VDD_NSP1_LEVEL>;//To-Do : Verify if VDD_NSP1_LEVEL should be used
		nsp-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		reg-names = "cx","mx","nsp";

		qcom,qmp = <&aoss_qmp>;

		memory-region = <&cdsp_mem &q6_cdsp_dtb_mem &global_sync_mem>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,
				<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		/* Inputs from turing */
		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					<&cdsp_smp2p_in 0 0>,
					<&cdsp_smp2p_in 2 0>,
					<&cdsp_smp2p_in 1 0>,
					<&cdsp_smp2p_in 3 0>,
					<&cdsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		remoteproc_cdsp_glink: glink-edge {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "cdsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_CDSP
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_cdsprm_rpmsg {
				compatible = "qcom,msm-cdsprm-rpmsg";
				qcom,glink-channels = "cdsprmglink-apps-dsp";
				qcom,intents = <0x20 12
						0xF00 12>;

				msm_cdsp_rm: qcom,msm_cdsp_rm {
					compatible = "qcom,msm-cdsp-rm";
					qcom,qos-cores = <0 1>;
					qcom,qos-latency-us = <70>;
					qcom,qos-maxhold-ms = <20>;
				};
			};
		};
	};

	modem_pas: remoteproc-mss@04080000 {
		compatible = "qcom,tuna-modem-pas";
		reg = <0x4080000 0x10000>;
		status = "ok";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-supply = <&VDD_MODEM_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
		reg-names = "cx", "mx";

		qcom,qmp = <&aoss_qmp>;

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
				<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "rproc_ddr", "crypto_ddr";

		memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma &dsm_partition_1_mem>;

		/* Inputs from mss */
		interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
					<&modem_smp2p_in 0 0>,
					<&modem_smp2p_in 2 0>,
					<&modem_smp2p_in 1 0>,
					<&modem_smp2p_in 3 0>,
					<&modem_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to mss */
		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		glink-edge {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "mpss_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_MPSS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "modem";
			qcom,glink-label = "mpss";

			qcom,modem_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,modem_ds {
				qcom,glink-channels = "DS";
				qcom,intents = <0x4000 0x2>;
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};

		qcom,glinkpkt-qmc-dma {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
			qcom,glinkpkt-dev-name = "qmc_dma";
			qcom,glinkpkt-enable-ch-close;
		};

		qcom,glinkpkt-qmc-cma {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
			qcom,glinkpkt-dev-name = "qmc_cma";
			qcom,glinkpkt-enable-ch-close;
		};

		qcom,glinkpkt-xpan_control {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "bt_cp_ctrl";
			qcom,glinkpkt-dev-name = "bt_cp_ctrl";
		};
	};

	sys-pm-vx@c320000 {
		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-tuna";
		reg = <0xc320000 0x400>;
		qcom,qmp = <&aoss_qmp>;
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,tuna-tlmm";
		reg = <0x0f000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;
		qcom,gpios-reserved = <54 4 5 6 7 82 83>;
	};

	tlmm-vm-mem-access {
		compatible = "qcom,tlmm-vm-mem-access";
		qcom,master;
		tuivm {
			qcom,label = <0x08>;
			qcom,vmid = <45>;
			tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0
			     &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>;
		};
	};

	tlmm-vm-test {
		compatible = "qcom,tlmm-vm-test";
		qcom,master;
		tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0
		    &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>;
	};

	slimbam: bamdma@6c04000 {
		compatible = "qcom,bam-v1.7.0";
		reg = <0x6c04000 0x20000>, <0x6c8f000 0x1000>;
		reg-names = "bam", "bam_remote_mem";
		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
		num-channels  = <31>;
		#dma-cells = <1>;
		qcom,controlled-remotely;
		qcom,ee = <1>;
		qcom,num-ees = <2>;
	};

	slim_msm: slim@6c40000 {
		compatible = "qcom,slim-ngd-v1.5.0";
		reg = <0x6c40000 0x2c000>, <0x6c8E000 0x1000>;
		reg-names = "ctrl", "slimbus_remote_mem";
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&slimbam 3>, <&slimbam 4>;
		dma-names = "rx", "tx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	ipcc_mproc: qcom,ipcc@406000 {
		compatible = "qcom,ipcc";
		reg = <0x406000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	aoss_qmp: power-controller@c300000 {
		compatible = "qcom,aoss-qmp";
		reg = <0xc300000 0x400>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		#power-domain-cells = <1>;
		#clock-cells = <0>;
	};

	qmp_aop: qcom,qmp-aop {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	qmp_tme: qcom,qmp-tme {
		compatible = "qcom,qmp-mbox";
		qcom,remote-pid = <14>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		mbox-names = "tme_qmp";
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;

		label = "tme";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	qcom,tmecom-qmp-client {
		compatible = "qcom,tmecom-qmp-client";
		mboxes = <&qmp_tme 0>;
		mbox-names = "tmecom";
		label = "tmecom";
		depends-on-supply = <&qmp_tme>;
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};


	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_smem_mailbox_1_out: qcom,smp2p-smem-mailbox-1-out {
			qcom,entry-name = "smem-mailbox";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_smem_mailbox_1_in: qcom,smp2p-smem-mailbox-1-in {
			qcom,entry-name = "smem-mailbox";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-wpss {
		compatible = "qcom,smp2p";
		qcom,smem = <617>, <616>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
			IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <13>;

		wpss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		wpss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-soccp {
		compatible = "qcom,smp2p";
		qcom,smem = <617>, <616>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <19>;

		soccp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		soccp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	eud: qcom,msm-eud@88e0000 {
		compatible = "qcom,msm-eud";
		interrupt-names = "eud_irq";
		interrupt-parent = <&pdc>;
		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x88e0000 0x2000>,
			<0x88e2000 0x1000>;
		reg-names = "eud_base", "eud_mode_mgr2";
		qcom,secure-eud-en;
		qcom,eud-utmi-delay = /bits/ 16 <255>;
		status = "ok";
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem_heap>;
		restrict-access;
	};

	wpss_pas: remoteproc-wpss@97000000 {
		compatible = "qcom,tuna-wpss-pas";
		reg = <0x97000000 0x10000>;
		status = "ok";

		memory-region = <&wpss_mem>;

		firmware-name = "wcn7750/wpss.mdt";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-supply = <&VDD_MX_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		reg-names = "cx","mx";

		qcom,qmp = <&aoss_qmp>;

		/* Inputs from wpss */
		interrupts-extended = <&intc GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
				      <&wpss_smp2p_in 0 0>,
				      <&wpss_smp2p_in 2 0>,
				      <&wpss_smp2p_in 1 0>,
				      <&wpss_smp2p_in 3 0>,
				      <&wpss_smp2p_in 7 0>;

		interrupt-names = "wdog",
				   "fatal",
				   "handover",
				   "ready",
				   "stop-ack",
				   "shutdown-ack";

		/* Outputs to wpss */
		qcom,smem-states = <&wpss_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		glink-edge {
			qcom,remote-pid = <13>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "wpss_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_WPSS
					  IPCC_MPROC_SIGNAL_GLINK_QMP
					  IRQ_TYPE_EDGE_RISING>;

			label = "wpss";
			qcom,glink-label = "wpss";

			qcom,wpss_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

		};

	};

	qcom,qrtr-mhi-cnss {
		compatible = "qcom,qrtr-mhi";
		qcom,dev-id = <0x1103>;
		qcom,net-id = <0>;
		qcom,low-latency;
	};

	qcom,qrtr-mhi-cnss {
		compatible = "qcom,qrtr-mhi";
		qcom,dev-id = <0x1107>;
		qcom,net-id = <1>;
		qcom,low-latency;
	};

	qfprom: qfprom@221c8000 {
		compatible = "qcom,tuna-qfprom", "qcom,qfprom";
		reg = <0x221c8000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		read-only;
		ranges;
		feat_conf6: feat_conf6@0118 {
			reg = <0x0118 0x4>;
		};

		gpu_speed_bin: gpu_speed_bin@138 {
			reg = <0x138 0x2>;
			bits = <0 9>;
		};

		feat_conf18: feat_conf18@0148 {
			reg = <0x0148 0x4>;
		};
	};

	qfprom_sys: qfprom@0 {
		compatible = "qcom,qfprom-sys";
		nvmem-cells = <&feat_conf6>, <&feat_conf18>;
		nvmem-cell-names = "feat_conf6", "feat_conf18";
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_0_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_1_clk";
			#clock-cells = <0>;
		};

		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_tx_symbol_0_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	cambistmclkcc: clock-controller@1760000 {
		compatible = "qcom,tuna-cambistmclkcc", "syscon";
		reg = <0x1760000 0x6000>;
		reg-name = "cc_base";
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&sleep_clk>,
			 <&gcc GCC_CAMERA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "sleep_clk",
			      "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cpuss-sleep-stats@17800054 {
		compatible = "qcom,cpuss-sleep-stats";
		reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
		      <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
		      <0x17860054 0x4>, <0x17870054 0x4>, <0x178a0098 0x4>,
		      <0x178c0000 0x10000>;
		reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
			    "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
			    "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
			    "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
			    "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
		num-cpus = <8>;
	};

	sram@c3f0000 {
		compatible = "qcom,rpmh-stats-v4";
		reg = <0x0c3f0000 0x400>;
		qcom,qmp = <&aoss_qmp>;
		ss-name = "modem", "wpss", "adsp", "adsp_island",
			  "cdsp", "apss";
	};

	cpufreq_hw: qcom,cpufreq-hw {
		compatible = "qcom,cpufreq-epss";
		reg = <0x17D91000 0x1000>, <0x17D92000 0x1000>,
		      <0x17D93000 0x1000>, <0x17D94000 0x1000>;
		reg-names = "freq-domain0", "freq-domain1",
			    "freq-domain2", "freq-domain3";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
		clock-names = "xo", "alternate";
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "dcvsh0_int",
				  "dcvsh1_int",
				  "dcvsh2_int",
				  "dcvsh3_int";
		#freq-domain-cells = <1>;
	};

	qcom,cpufreq-hw-debug {
		compatible = "qcom,cpufreq-hw-epss-debug";
		qcom,freq-hw-domain = <&cpufreq_hw 0>,
				      <&cpufreq_hw 1>,
				      <&cpufreq_hw 2>,
				      <&cpufreq_hw 3>;
	};

	camcc_crm: syscon@adcd600 {
		compatible = "syscon";
		reg = <0xadcd600 0x2000>;
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,tuna-camcc", "syscon";
		reg = <0xade0000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&sleep_clk>,
			 <&gcc GCC_CAMERA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "sleep_clk",
			      "iface";
		qcom,cam_crm-crmc = <&camcc_crm>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc_crm: syscon@af27800 {
		compatible = "syscon";
		reg = <0xaf27800 0x2000>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,tuna-dispcc-v1", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&rpmhcc RPMH_CXO_CLK_A>,
			 <&sleep_clk>,
			 <&gcc GCC_DISP_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "bi_tcxo_ao",
			      "sleep_clk",
			      "iface";
		qcom,disp_crm-crmc = <&dispcc_crm>;
		#power-domain-cells = <1>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	evacc: clock-controller@abf0000 {
		compatible = "qcom,tuna-evacc", "syscon";
		reg = <0xabf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&rpmhcc RPMH_CXO_CLK_A>,
			 <&sleep_clk>,
			 <&gcc GCC_EVA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "bi_tcxo_ao",
			      "sleep_clk",
			      "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,tuna-gcc-v1", "syscon";
		reg = <0x100000 0x1f4200>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&pcie_0_pipe_clk>,
			 <&sleep_clk>,
			 <&ufs_phy_rx_symbol_0_clk>,
			 <&ufs_phy_rx_symbol_1_clk>,
			 <&ufs_phy_tx_symbol_0_clk>,
			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
		clock-names = "bi_tcxo",
			      "pcie_0_pipe_clk",
			      "sleep_clk",
			      "ufs_phy_rx_symbol_0_clk",
			      "ufs_phy_rx_symbol_1_clk",
			      "ufs_phy_tx_symbol_0_clk",
			      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,tuna-gpucc", "syscon";
		reg = <0x3d90000 0x9800>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
			 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
		clock-names = "bi_tcxo",
			      "gpll0_out_main",
			      "gpll0_out_main_div";
		#clock-cells = <1>;
		#reset-cells = <1>;
		#power-domain-cells = <1>;
	};

	gxclkctl: clock-controller@3d68024 {
		compatible = "qcom,tuna-gx_clkctl";
		reg = <0x3d68024 0x8>;
		reg-name = "cc_base";
		power-domains = <&gpucc GPU_CC_CX_GDSC>;
		vdd_gx-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
		#power-domain-cells = <1>;
	};

	tcsrcc: clock-controller@1fbf000 {
		compatible = "qcom,tuna-tcsrcc", "syscon";
		reg = <0x1fbf000 0x14>;
		reg-name = "cc_base";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@aaf0000 {
		compatible = "qcom,tuna-videocc", "syscon";
		reg = <0xaaf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		vdd_mm_mxc_voter-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&rpmhcc RPMH_CXO_CLK_A>,
			 <&sleep_clk>,
			 <&gcc GCC_VIDEO_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "bi_tcxo_ao",
			      "sleep_clk",
			      "iface";
		#power-domain-cells = <1>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	apsscc: syscon@17a80000 {
		compatible = "syscon";
		reg = <0x17a80000 0x31000>;
	};

	mccc: syscon@240ba000 {
		compatible = "syscon";
		reg = <0x240ba000 0x54>;
	};

	gxclkctldebugcc: syscon@3d64000 {
		compatible = "syscon";
		reg = <0x3d64000 0x6000>;
	};

	debugcc: clock-controller@0 {
		compatible = "qcom,tuna-debugcc";
		qcom,apsscc = <&apsscc>;
		qcom,cambistmclkcc = <&cambistmclkcc>;
		qcom,camcc = <&camcc>;
		qcom,dispcc = <&dispcc>;
		qcom,evacc = <&evacc>;
		qcom,gcc = <&gcc>;
		qcom,gpucc = <&gpucc>;
		qcom,gxclkctl = <&gxclkctldebugcc>;
		qcom,videocc = <&videocc>;
		qcom,mccc = <&mccc>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&cambistmclkcc 0>,
			 <&camcc 0>, <&dispcc 0>,
			 <&evacc 0>, <&gcc 0>,
			 <&gpucc 0>, <&gxclkctl 0>,
			 <&videocc 0>;
		clock-names = "xo_clk_src", "cambistmclkcc",
			      "camcc", "dispcc",
			      "evacc", "gcc",
			      "gpucc", "gxclkctl",
			      "videocc";
		#clock-cells = <1>;
	};

	tcsr: syscon@1fc0000 {
		compatible = "syscon";
		reg = <0x1fc0000 0x30000>;
	};

	qcom,msm-imem@14680000 {
		compatible = "qcom,msm-imem";
		reg = <0x14680000 0x1000>;
		ranges = <0x0 0x14680000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,pil-reloc-info";
			reg = <0x94c 0xc8>;
		};

		pil@6dc {
			compatible = "qcom,msm-imem-pil-disable-timeout";
			reg = <0x6dc 0x4>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};

		modem_dsm@c98 {
			compatible = "qcom,msm-imem-mss-dsm";
			reg = <0xc98 0x10>;
		};

		sys_dbg@af8 {
			compatible = "qcom,msm-imem-gpu-dump-skip";
			reg = <0xb0c 0x4>;
		};
	};

	google,debug-kinfo {
		compatible = "google,debug-kinfo";
		memory-region = <&kinfo_mem>;
	};

	mini_dump_mode {
		compatible = "qcom,minidump";
		status = "ok";
	};

	va_mini_dump {
		compatible = "qcom,va-minidump";
		memory-region = <&va_md_mem>;
		status = "ok";
	};

	qcom_ramoops {
		compatible = "qcom,ramoops";
		memory-region = <&ramoops_mem>;
		pmsg-size = <0x200000>;
		mem-type = <2>;
	};

	qcom,mpm2-sleep-counter@c221000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	qti,smmu-proxy {
		compatible = "smmu-proxy-sender";
	};

	pcie_crm_hw_0_bcm_voter: bcm_voter@0 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "pcie_crm";
		qcom,crm-client-idx = <0>;
		qcom,crm-pwr-states = <5>;
	};

	disp_crm_hw_0_bcm_voter: bcm_voter@1 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "disp_crm";
		qcom,crm-client-idx = <0>;
		qcom,crm-pwr-states = <2>;
	};

	disp_crm_hw_1_bcm_voter: bcm_voter@2 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "disp_crm";
		qcom,crm-client-idx = <1>;
		qcom,crm-pwr-states = <2>;
	};

	disp_crm_hw_2_bcm_voter: bcm_voter@3 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "disp_crm";
		qcom,crm-client-idx = <2>;
		qcom,crm-pwr-states = <2>;
	};

	disp_crm_hw_3_bcm_voter: bcm_voter@4 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "disp_crm";
		qcom,crm-client-idx = <3>;
		qcom,crm-pwr-states = <2>;
	};

	disp_crm_hw_4_bcm_voter: bcm_voter@5 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "disp_crm";
		qcom,crm-client-idx = <4>;
		qcom,crm-pwr-states = <2>;
	};

	disp_crm_hw_5_bcm_voter: bcm_voter@6 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "disp_crm";
		qcom,crm-client-idx = <5>;
		qcom,crm-pwr-states = <2>;
	};

	disp_crm_sw_0_bcm_voter: bcm_voter@7 {
		compatible = "qcom,bcm-voter";
		qcom,crm-name = "disp_crm";
		qcom,crm-sw-client;
		qcom,crm-client-idx = <0>;
		qcom,crm-pwr-states = <1>;
	};

	clk_virt: interconnect@0 {
		compatible = "qcom,tuna-clk_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos",
				       "pcie_crm_hw_0";
		qcom,bcm-voters = <&apps_bcm_voter>,
				  <&pcie_crm_hw_0_bcm_voter>;
	};

	mc_virt: interconnect@1 {
		compatible = "qcom,tuna-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos",
				       "cam_ife_0",
				       "cam_ife_1",
				       "cam_ife_2",
				       "pcie_crm_hw_0",
				       "disp_crm_hw_0",
				       "disp_crm_hw_1",
				       "disp_crm_hw_2",
				       "disp_crm_hw_3",
				       "disp_crm_hw_4",
				       "disp_crm_hw_5",
				       "disp_crm_sw_0";
		qcom,bcm-voters = <&apps_bcm_voter>,
				  <&cam_bcm_voter0>,
				  <&cam_bcm_voter1>,
				  <&cam_bcm_voter2>,
				  <&pcie_crm_hw_0_bcm_voter>,
				  <&disp_crm_hw_0_bcm_voter>,
				  <&disp_crm_hw_1_bcm_voter>,
				  <&disp_crm_hw_2_bcm_voter>,
				  <&disp_crm_hw_3_bcm_voter>,
				  <&disp_crm_hw_4_bcm_voter>,
				  <&disp_crm_hw_5_bcm_voter>,
				  <&disp_crm_sw_0_bcm_voter>;
	};

	config_noc: interconnect@1600000 {
		compatible = "qcom,tuna-cnoc_cfg";
		reg = <0x1600000 0x9200>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	cnoc_main: interconnect@1500000 {
		compatible = "qcom,tuna-cnoc_main";
		reg = <0x1500000 0x16080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	system_noc: interconnect@1680000 {
		compatible = "qcom,tuna-system_noc";
		reg = <0x1680000 0x1d080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	pcie_noc: interconnect@16c0000 {
		compatible = "qcom,tuna-pcie_anoc";
		reg = <0x16c0000 0x11400>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos",
				       "pcie_crm_hw_0";
		qcom,bcm-voters = <&apps_bcm_voter>,
				  <&pcie_crm_hw_0_bcm_voter>;
		qcom,skip-qos;
	};

	aggre1_noc: interconnect@16e0000 {
		compatible = "qcom,tuna-aggre1_noc";
		reg = <0x16e0000 0x16400>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	aggre2_noc: interconnect@1700000 {
		compatible = "qcom,tuna-aggre2_noc";
		reg = <0x1700000 0x1f400>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	mmss_noc: interconnect@1780000 {
		compatible = "qcom,tuna-mmss_noc";
		reg = <0x1780000 0x7d800>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos",
				       "cam_ife_0",
				       "cam_ife_1",
				       "cam_ife_2",
				       "disp_crm_hw_0",
				       "disp_crm_hw_1",
				       "disp_crm_hw_2",
				       "disp_crm_hw_3",
				       "disp_crm_hw_4",
				       "disp_crm_hw_5",
				       "disp_crm_sw_0";
		qcom,bcm-voters = <&apps_bcm_voter>,
				  <&cam_bcm_voter0>,
				  <&cam_bcm_voter1>,
				  <&cam_bcm_voter2>,
				  <&disp_crm_hw_0_bcm_voter>,
				  <&disp_crm_hw_1_bcm_voter>,
				  <&disp_crm_hw_2_bcm_voter>,
				  <&disp_crm_hw_3_bcm_voter>,
				  <&disp_crm_hw_4_bcm_voter>,
				  <&disp_crm_hw_5_bcm_voter>,
				  <&disp_crm_sw_0_bcm_voter>;
		qcom,skip-qos;
	};

	gem_noc: interconnect@24100000 {
		compatible = "qcom,tuna-gem_noc";
		reg = <0x24100000 0x14d080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos",
				       "cam_ife_0",
				       "cam_ife_1",
				       "cam_ife_2",
				       "pcie_crm_hw_0",
				       "disp_crm_hw_0",
				       "disp_crm_hw_1",
				       "disp_crm_hw_2",
				       "disp_crm_hw_3",
				       "disp_crm_hw_4",
				       "disp_crm_hw_5",
				       "disp_crm_sw_0";
		qcom,bcm-voters = <&apps_bcm_voter>,
				  <&cam_bcm_voter0>,
				  <&cam_bcm_voter1>,
				  <&cam_bcm_voter2>,
				  <&pcie_crm_hw_0_bcm_voter>,
				  <&disp_crm_hw_0_bcm_voter>,
				  <&disp_crm_hw_1_bcm_voter>,
				  <&disp_crm_hw_2_bcm_voter>,
				  <&disp_crm_hw_3_bcm_voter>,
				  <&disp_crm_hw_4_bcm_voter>,
				  <&disp_crm_hw_5_bcm_voter>,
				  <&disp_crm_sw_0_bcm_voter>;
		qcom,skip-qos;
	};

	nsp_noc: interconnect@320c0000 {
		compatible = "qcom,tuna-nsp_noc";
		reg = <0x320c0000 0xe080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	lpass_ag_noc: interconnect@7e40000 {
		compatible = "qcom,tuna-lpass_ag_noc";
		reg = <0x7e40000 0xe080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	lpass_lpiaon_noc: interconnect@7400000 {
		compatible = "qcom,tuna-lpass_lpiaon_noc";
		reg = <0x7400000 0x19080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	lpass_lpicx_noc: interconnect@7420000 {
		compatible = "qcom,tuna-lpass_lpicx_noc";
		reg = <0x7420000 0x44080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x400000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
	};

	sdhc2_opp_table: sdhc2-opp-table {
		compatible = "operating-points-v2";

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-peak-kBps = <160000 100000>;
			opp-avg-kBps = <50000 0>;
		};

		opp-202000000 {
			opp-hz = /bits/ 64 <202000000>;
			opp-peak-kBps = <200000 120000>;
			opp-avg-kBps = <104000 0>;
		};
	};

	sdhc_2_dma_resv: sdhc_2_dma_resv_region {
		/*
		 * Restrict IOVA mappings for SDHC2 buffers to the 256 MB region
		 * from 0x40000000 - 0x4fffffff.
		 */
		iommu-addresses = <&sdhc_2 0x0 0x40000000>,
				  <&sdhc_2 0x50000000 0xb0000000>;
	};

	sdhc_2: sdhci@8804000 {
		status = "disabled";

		compatible = "qcom,sdhci-msm-v5";
		reg = <0x08804000 0x1000>;
		reg-names = "hc";

		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		bus-width = <4>;
		no-sdio;
		no-mmc;
		qcom,restore-after-cx-collapse;

		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface", "core";

		/*
		 * DLL HSR settings. Refer go/hsr - <Target> DLL settings.
		 * Note that the DLL_CONFIG_2 value is not passed from the
		 * device tree, but it is calculated in the driver.
		 */
		qcom,dll-hsr-list = <0x0007442C 0x0 0x10
					0x090106C0 0x80040868>;

		iommus = <&apps_smmu 0x140 0x0>;
		qcom,iommu-dma = "fastmap";
		dma-coherent;
		memory-region = <&sdhc_2_dma_resv>;

		interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
			      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";
		operating-points-v2 = <&sdhc2_opp_table>;

		resets = <&gcc GCC_SDCC2_BCR>;
		reset-names = "core_reset";

		qos0 {
			mask = <0xc0>;
			vote = <44>;
		};

		qos1 {
			mask = <0x3f>;
			vote = <44>;
		};
	};

	ufsphy_mem: ufsphy_mem@1d80000 {
		reg = <0x1d80000 0x2000>;
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;
		clock-names = "ref_clk_src",
			"ref_aux_clk", "qref_clk",
			"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
			"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
		clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
			<&tcsrcc TCSR_UFS_CLKREF_EN>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
			<&ufs_phy_rx_symbol_0_clk>,
			<&ufs_phy_rx_symbol_1_clk>,
			<&ufs_phy_tx_symbol_0_clk>;
		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	ice_cfg: shared_ice {
		 alg1 {
		      alg-name = "alg1";
		      rx-alloc-percent = <60>;
		      status = "disabled";
		 };

		 alg2 {
		      alg-name = "alg2";
		      status = "disabled";

		 };

		 alg3 {
		      alg-name = "alg3";
		      num-core = <28 28 15 13>;
		      status = "ok";
		 };
	};

	ufshc_dma_resv: ufshc_dma_resv_region {
		/*
		 * Restrict IOVA mappings for UFSHC buffers to the 3 GB region
		 * from 0x1000 - 0xffffffff.
		 */
		iommu-addresses = <&ufshc_mem 0x0 0x1000>;
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>,
			<0x1d88000 0x18000>,
			<0x1da5000 0x2000>,
			<0x1da4000 0x10>;
		reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs";

		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;

		qcom,ice-use-hwkm;
		qcom,prime-mask = <0x80>;
		qcom,silver-mask = <0x0f>;
		qcom,esi-affinity-mask = <1 1 4 4 3 6 6 7>;

		lanes-per-direction = <2>;
		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_LN_BB_CLK3>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<100000000 403000000>,
			<0 0>,
			<0 0>,
			<100000000 403000000>,
			<100000000 403000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		/* set the dependency that smmu being probed before ufs */
		depends-on-supply = <&apps_smmu>;

		iommus = <&apps_smmu 0x60 0x0>;
		qcom,iommu-dma = "fastmap";
		qcom,iommu-msi-size = <0x1000>;
		memory-region = <&ufshc_dma_resv>;
		shared-ice-cfg = <&ice_cfg>;
		dma-coherent;

		qcom,bypass-pbl-rst-wa;
		qcom,max-cpus = <8>;

		msi-parent = <&gic_its 0x60>;

		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";

		status = "disabled";

		qos0 {
			mask = <0xfc>;
			vote = <44>;
			perf;
			cpu_freq_vote = <2 5 7>;
		};

		qos1 {
			mask = <0x03>;
			vote = <44>;
			cpu_freq_vote = <0>;
		};
	};

	qcom_tzlog: tz-log@14680720 {
		compatible = "qcom,tz-log";
		reg = <0x14680720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
		tmecrashdump-address-offset = <0x81CA0000>;
	};

	qcom_cedev: qcedev@1de0000 {
		compatible = "qcom,qcedev";
		reg = <0x1de0000 0x20000>,
			<0x1dc4000 0x28000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <2>;
		qcom,offload-ops-support;
		qcom,bam-pipe-offload-cpb-hlos = <1>;
		qcom,bam-pipe-offload-hlos-cpb = <3>;
		qcom,bam-pipe-offload-hlos-cpb-1 = <8>;
		qcom,bam-pipe-offload-hlos-hlos = <4>;
		qcom,bam-pipe-offload-hlos-hlos-1 = <9>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,bam-ee = <0>;
		qcom,smmu-s1-enable;
		qcom,no-clock-support;
		qcom,no-clk-gating;
		interconnect-names = "data_path";
		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		iommus = <&apps_smmu 0x0480 0x0>,
			<&apps_smmu 0x0481 0x0>;
		qcom,iommu-dma = "atomic";
		dma-coherent;

		qcom_cedev_ns_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "ns_context";
			iommus = <&apps_smmu 0x0481 0x0>;
			dma-coherent;
		};

		qcom_cedev_s_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "secure_context";
			iommus = <&apps_smmu 0x0483 0x0>;
			qcom,iommu-vmid = <0x9>;
			qcom,secure-context-bank;
			dma-noncoherent;
		};
	};

	rng: rng@10c3000 {
		compatible = "qcom,trng";
		reg = <0x10c3000 0x1000>;
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
		compatible = "qcom,spmi-pmic-arb";
			reg = <0xc42d000 0x4000>,
			<0xc400000 0x3000>,
			<0xc500000 0x400000>,
			<0xc440000 0x80000>,
			<0xc4c0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <0>;
	};

	spmi1_bus: qcom,spmi@c432000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc432000 0x4000>,
			<0xc400000 0x3000>,
			<0xc500000 0x400000>,
			<0xc440000 0x80000>,
			<0xc4d0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <1>;
		depends-on-supply = <&spmi0_bus>;
		status = "disabled";
	};

	spmi0_debug_bus: qcom,spmi-debug@10b14000 {
		compatible = "qcom,spmi-pmic-arb-debug";
		reg = <0x10b14000 0x60>, <0x221c8784 0x4>;
		reg-names = "core", "fuse";
		clocks = <&aoss_qmp>;
		clock-names = "core_clk";
		qcom,fuse-enable-bit = <18>;
		#address-cells = <2>;
		#size-cells = <0>;
		depends-on-supply = <&spmi_bus>;

		pmk8550@0 {
			compatible = "qcom,spmi-pmic";
			reg = <0 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pmxr2230@1 {
			compatible = "qcom,spmi-pmic";
			reg = <1 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8550vs@3 {
			compatible = "qcom,spmi-pmic";
			reg = <3 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8550ve@5 {
			compatible = "qcom,spmi-pmic";
			reg = <5 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8550vs@6 {
			compatible = "qcom,spmi-pmic";
			reg = <6 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pmg1110@8 {
			compatible = "qcom,spmi-pmic";
			reg = <8 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
			status = "disabled";
		};

		pmg1110@9 {
			compatible = "qcom,spmi-pmic";
			reg = <9 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
			status = "disabled";
		};

		pmr735d@a {
			compatible = "qcom,spmi-pmic";
			reg = <10 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8010@c {
			compatible = "qcom,spmi-pmic";
			reg = <12 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8010@d {
			compatible = "qcom,spmi-pmic";
			reg = <13 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

	};

	thermal_zones: thermal-zones {
	};

	qcom,pmic_glink {
		compatible = "qcom,qti-pmic-glink";
		qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
		qcom,subsys-name = "lpass";
		qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
		depends-on-supply = <&ipcc_mproc>;

		battery_charger: qcom,battery_charger {
			compatible = "qcom,battery-charger";
		};

		ucsi: qcom,ucsi {
			compatible = "qcom,ucsi-glink";
			connector {
				port {
					usb_port0_connector: endpoint {
					remote-endpoint = <&usb_port0>;
					};
				};
			};
		};

		altmode: qcom,altmode {
			compatible = "qcom,altmode-glink";
			#altmode-cells = <1>;
		};
	};


	qcom,qrtr-gunyah-oemvm {
		compatible = "qcom,qrtr-gunyah";
		qcom,master;
		gunyah-label = <8>;
		peer-name = <4>;
	};

	trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring {
		size = <0x4000>;
		gunyah-label = <0x11>;
	};

	trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring {
		size = <0x4000>;
		gunyah-label = <0x10>;
	};


	trust_ui_vm_vsock_ring: trust_ui_vm_vsock_ring {
		size = <0xc000>;
		gunyah-label = <0x15>;
	};

	trust_ui_vm_swiotlb: trust_ui_vm_swiotlb {
		size = <0x400000>;
		gunyah-label = <0x12>;
	};

	trust_ui_vm: qcom,trust_ui_vm {
		vm_name = "trustedvm";
		shared-buffers-size = <0x414000>;
		shared-buffers = <&trust_ui_vm_vblk0_ring
				&trust_ui_vm_vblk1_ring
				&trust_ui_vm_vsock_ring
				&trust_ui_vm_swiotlb>;
	};

	trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 {
		qcom,vm = <&trust_ui_vm>;
		qcom,label = <0x11>;
	};

	trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 {
		qcom,vm = <&trust_ui_vm>;
		qcom,label = <0x10>;
	};

	trust_ui_vm_virt_be2: trust_ui_vm_virt_be2@15 {
		qcom,vm = <&trust_ui_vm>;
		qcom,label = <0x15>;
	};

	gh-secure-vm-loader@0 {
		compatible = "qcom,gh-secure-vm-loader";
		qcom,pas-id = <28>;
		qcom,vmid = <45>;
		qcom,firmware-name = "trustedvm";
		qcom,keep-running;
		memory-region = <&trust_ui_vm_mem &vm_comm_mem>;
		virtio-backends = <&trust_ui_vm_virt_be0
				&trust_ui_vm_virt_be1
				&trust_ui_vm_virt_be2>;
	};

	oem_vm_vblk0_ring: oem_vm_vblk0_ring {
		size = <0x4000>;
		gunyah-label = <0x16>;
	};

	oem_vm_vblk1_ring: oem_vm_vblk1_ring {
		size = <0x4000>;
		gunyah-label = <0x13>;
	};

	oem_vm_swiotlb: oem_vm_swiotlb {
		size = <0x100000>;
		gunyah-label = <0x14>;
	};

	oem_vm: qcom,oem_vm {
		vm_name = "oemvm";
		shared-buffers-size = <0x108000>;
		shared-buffers = <&oem_vm_vblk0_ring &oem_vm_vblk1_ring &oem_vm_swiotlb>;
	};

	oem_vm_virt_be0: oem_vm_virt_be0@16 {
		qcom,vm = <&oem_vm>;
		qcom,label = <0x16>;
	};

	oem_vm_virt_be1: oem_vm_virt_be1@13 {
		qcom,vm = <&oem_vm>;
		qcom,label = <0x13>;
	};

	gh-secure-vm-loader@1 {
		compatible = "qcom,gh-secure-vm-loader";
		qcom,pas-id = <34>;
		qcom,vmid = <49>;
		qcom,firmware-name = "oemvm";
		qcom,keep-running;
		memory-region = <&oem_vm_mem &vm_comm_mem>;
		virtio-backends = <&oem_vm_virt_be0 &oem_vm_virt_be1>;
	};

	gh-secure-vm-loader@2 {
		compatible = "qcom,gh-secure-vm-loader";
		qcom,pas-id = <35>;
		qcom,vmid = <50>;
		qcom,firmware-name = "cpusys_vm";
		memory-region = <&cpusys_vm_mem>;
		ext-region = <&chipinfo_mem>;
		ext-label = <0x7>;
		status = "disabled";
	};

	qcom,qrtr-gunyah-tuivm {
		compatible = "qcom,qrtr-gunyah";
		qcom,master;
		gunyah-label = <3>;
		peer-name = <2>;
	};

	qcom,pmic_glink_log {
		compatible = "qcom,qti-pmic-glink";
		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";

		qcom,battery_debug {
			compatible = "qcom,battery-debug";
		};

		qcom,charger_ulog_glink {
			compatible = "qcom,charger-ulog-glink";
		};

		pmic_glink_debug: qcom,pmic_glink_debug {
			compatible = "qcom,pmic-glink-debug";
			#address-cells = <1>;
			#size-cells = <0>;
			depends-on-supply = <&spmi1_bus>;

		};

		pmic_glink_adc: qcom,glink-adc {
			compatible = "qcom,glink-adc";
			#address-cells = <1>;
			#size-cells = <0>;
			#io-channel-cells = <1>;
			status = "disabled";
		};
	};

	qcom,test-dbl-tuivm {
		compatible = "qcom,gh-dbl";
		qcom,label = <0x4>;
	};

	qcom,test-dbl-oemvm {
		compatible = "qcom,gh-dbl";
		qcom,label = <0x5>;
	};

	qcom,test-msgq-tuivm {
		compatible = "qcom,gh-msgq-test";
		gunyah-label = <0x4>;
		qcom,primary;
	};

	qcom,test-msgq-oemvm {
		compatible = "qcom,gh-msgq-test";
		gunyah-label = <0x5>;
		qcom,primary;
	};

	qcom,test-large-dmabuf-tuivm {
		compatible = "qcom,gh-large-dmabuf-test";
		gunyah-label = <0xd>;
		qcom,primary;
	};

	qcom,test-large-dmabuf-oemvm {
		compatible = "qcom,gh-large-dmabuf-test";
		gunyah-label = <0xe>;
		qcom,primary;
	};

	qcom,gh-qtimer@1742b000 {
		compatible = "qcom,gh-qtmr";
		reg = <0x1742b000 0x1000>;
		reg-names = "qtmr-base";
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "qcom,qtmr-intr";
		qcom,primary;
	};

	qcom,gunyah-panic-notifier {
		compatible = "qcom,gh-panic-notifier";
		qcom,primary-vm;
		gunyah-label = <9>;
		peer-name = <2>;
		memory-region = <&vm_comm_mem>;
		shared-buffer-size = <0x1000>;
	};

	dmesg-dump {
		compatible = "qcom,dmesg-dump";
		qcom,primary-vm;
		gunyah-label = <7>;
		peer-name = <2>;
		memory-region = <&vm_comm_mem>;
		shared-buffer-size = <0x1000>;
	};

	mmio_sram: mmio-sram@17D09400 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "mmio-sram";
		reg = <0x0 0x17D09400 0x0 0x400>;
		ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>;

		cpu_scp_lpri: scmi-shmem@0 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x17D09400 0x0 0x400>;
		};
	};

	cpucp: qcom,cpucp@17400000 {
		compatible = "qcom,cpucp";
		reg =   <0x17d90000 0x2000>,
			<0x17400000 0x10>;
		reg-names = "rx", "tx";
		#mbox-cells = <1>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	};

	scmi: qcom,scmi {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,scmi";
		mboxes = <&cpucp 0>;
		mbox-names = "tx";
		shmem = <&cpu_scp_lpri>;

		scmi_qcom: protocol@80 {
			reg = <0x80>;
			#clock-cells = <1>;
		};
	};

	cpucp_log: qcom,cpucp_log@d8140000 {
		compatible = "qcom,cpucp-log";
		reg = <0x81200000 0x10000>, <0x81210000 0x10000>;
		mboxes = <&cpucp 1>;
	};

	qcom_c1dcvs: qcom,c1dcvs {
		compatible = "qcom,c1dcvs-v2";
	};

	qcom_dynpf: qcom,dynpf {
		compatible = "qcom,dynpf";
	};

	qcom_cpufreq_stats: qcom,cpufreq_stats {
		compatible = "qcom,cpufreq-stats-v2";
	};

	qcom_mpam: qcom,mpam {
		compatible = "qcom,mpam";
	};

	cpu_mpam: qcom,cpu_mpam {
		compatible = "qcom,cpu-mpam";

		L3 {
			qcom,msc-id = <0>;
			qcom,msc-name = "L3";
		};
	};

	noc_bw_mpam: qcom,noc_bw_mpam {
		compatible = "qcom,platform-mpam";
		reg = <0x17D2E800 0x400>;
		reg-names = "mon-base";
		qcom,msc-id = <3>;
		qcom,msc-name = "noc_bw";
		qcom,gears = "low", "medium", "high", "veryhigh";
		qcom,gear-id = <1>, <2>, <3>, <4>;

		cpu {
			qcom,client-id = <0x1>;
			qcom,client-name = "cpu";
		};

		gpu {
			qcom,client-id = <0x10>;
			qcom,client-name = "gpu";
		};

		nsp {
			qcom,client-id = <0x100>;
			qcom,client-name = "nsp";
		};
	};

	llcc_pmu: llcc-pmu@24095000 {
		compatible = "qcom,llcc-pmu-ver2";
		reg = <0x24095000 0x300>;
		reg-names = "lagg-base";
	};

	qcom_pmu: qcom,pmu {
		compatible = "qcom,pmu";
		qcom,long-counter;
		qcom,pmu-events-tbl =
			< 0x0008 0xFF 0x02 0xFF >,
			< 0x0011 0xFF 0x01 0xFF >,
			< 0x0017 0xFF 0xFF 0xFF >,
			< 0x0037 0xFF 0xFF 0xFF >,
			< 0x1000 0xFF 0xFF 0xFF >;
	};

	ddr_freq_table: ddr-freq-table {
		qcom,freq-tbl =
			<  547000 >,
			< 1353600 >,
			< 1555200 >,
			< 1708000 >,
			< 2092800 >,
			< 2736000 >,
			< 3187200 >,
			< 3686400 >,
			< 4224000 >,
			< 4761600 >;
	};

	llcc_freq_table: llcc-freq-table {
		qcom,freq-tbl =
			<  350000 >,
			<  533000 >,
			<  600000 >,
			<  806000 >,
			<  933000 >,
			< 1066000 >,
			< 1211200 >;
	};

	ddrqos_freq_table: ddrqos-freq-table {
		qcom,freq-tbl =
			< 0 >,
			< 1 >;
	};

	qcom_dcvs: qcom,dcvs {
		compatible = "qcom,dcvs";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		qcom_l3_dcvs_hw: l3 {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <2>;
			qcom,bus-width = <32>;
			reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
			reg-names = "l3-base", "l3tbl-base";

			l3_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				qcom,shared-offset = <0x0090>;
			};
		};

		qcom_ddr_dcvs_hw: ddr {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <0>;
			qcom,bus-width = <4>;
			qcom,freq-tbl = <&ddr_freq_table>;

			ddr_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&mc_virt MASTER_LLCC
						 &mc_virt SLAVE_EBI1>;
			};

			ddr_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};
		};

		qcom_llcc_dcvs_hw: llcc {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <1>;
			qcom,bus-width = <16>;
			qcom,freq-tbl = <&llcc_freq_table>;

			llcc_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&gem_noc MASTER_APPSS_PROC
						 &gem_noc SLAVE_LLCC>;
			};

			llcc_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};
		};

		qcom_ddrqos_dcvs_hw: ddrqos {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <3>;
			qcom,bus-width = <1>;
			qcom,freq-tbl = <&ddrqos_freq_table>;

			ddrqos_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&mc_virt MASTER_LLCC
						 &mc_virt SLAVE_EBI1>;
			};
		};
	};

	qcom_memlat: qcom,memlat {
		compatible = "qcom,memlat";

		ddr {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
			qcom,sampling-path = <&ddr_dcvs_fp>;
			qcom,miss-ev = <0x1000>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,cpufreq-memfreq-tbl =
					< 1075200  547000 >,
					< 1401600 1555000 >,
					< 2016000 2092000 >;
				qcom,sampling-enabled;
			};

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
				qcom,cpufreq-memfreq-tbl =
					<  633600  547000 >,
					<  940800 1555000 >,
					< 1190400 1708000 >,
					< 1401600 2092000 >,
					< 1824000 2736000 >,
					< 2073600 3187200 >,
					< 2803200 3686400 >,
					< 2918400 4224000 >,
					< 3014400 4700000 >;
				qcom,sampling-enabled;
			};

			prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					<  633600  547000 >,
					<  960000 1555000 >,
					< 1228800 1708000 >,
					< 1478400 2092000 >,
					< 2169600 3187200 >,
					< 2956800 3686400 >,
					< 3187200 4224000 >,
					< 3206400 4700000 >;
				qcom,sampling-enabled;
			};

			gold-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 2073600  547000 >,
					< 3187200 2092000 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};

			prime-latfloor {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 2169600  547000 >,
					< 2956800 2092000 >,
					< 3206400 4224000 >;
				qcom,sampling-enabled;
			};
		};

		llcc {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
			qcom,sampling-path = <&llcc_dcvs_fp>;
			qcom,miss-ev = <0x37>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,cpufreq-memfreq-tbl =
					<  883200  350000 >,
					< 1401600  533000 >,
					< 2016000  600000 >;
				qcom,sampling-enabled;
			};

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					<  633600  350000 >,
					< 1190400  533000 >,
					< 1401600  600000 >,
					< 1824000  806000 >,
					< 2803200  933000 >,
					< 2918400 1066000 >,
					< 3014400 1211000 >;
				qcom,sampling-enabled;
			};

			gold-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 2073600  350000 >,
					< 3014400  600000 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};
		};

		l3 {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_l3_dcvs_hw>;
			qcom,sampling-path = <&l3_dcvs_sp>;
			qcom,miss-ev = <0x17>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,cpufreq-memfreq-tbl =
					<  364800  364800 >,
					<  614400  518400 >,
					<  748800  614400 >,
					<  883200  806400 >,
					<  979200  902400 >,
					< 1075200  998400 >,
					< 1286400 1209600 >,
					< 1401600 1344000 >,
					< 1632000 1497600 >,
					< 1785600 1593600 >,
					< 2016000 1804800 >;
				qcom,sampling-enabled;
			};

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
				qcom,cpufreq-memfreq-tbl =
					<  480000  364800 >,
					<  633600  518400 >,
					<  940800  614400 >,
					< 1190400  902400 >,
					< 1401600  998400 >,
					< 1632000 1209600 >,
					< 2073600 1344000 >,
					< 2438400 1497600 >,
					< 2803200 1593600 >,
					< 3014400 1804800 >;
				qcom,sampling-enabled;
			};

			prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					<  480000  364800 >,
					<  633600  518400 >,
					<  940800  614400 >,
					< 1228800  902400 >,
					< 1478400 1209600 >,
					< 1920000 1344000 >,
					< 2169600 1497600 >,
					< 2515200 1593600 >,
					< 3206400 1804800 >;
				qcom,sampling-enabled;
			};

			prime-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 1920000  364800 >,
					< 2512200 1209600 >,
					< 3206400 1804800 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};
		};

		ddrqos {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
			qcom,sampling-path = <&ddrqos_dcvs_sp>;
			qcom,miss-ev = <0x1000>;

			ddrqos_gold_lat: gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 2073600 0 >,
					< 3014400 1 >;
				qcom,sampling-enabled;
			};

			ddrqos_prime_lat: prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 1478400 0 >,
					< 3206400 1 >;
				qcom,sampling-enabled;
			};

			ddrqos_prime_latfloor: prime-latfloor {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 2169600 0 >,
					< 3206400 1 >;
				qcom,sampling-enabled;
			};
		};
	};

	qcom_llcc_l3_vote: qcom,llcc-l3-vote {
		qcom,target-dev = <&qcom_l3_dcvs_hw>;
		qcom,secondary-map =
			<  350000  364800 >,
			<  533000  518400 >,
			<  600000  614400 >,
			<  806000  806400 >,
			<  933000  902400 >,
			< 1066000  998400 >,
			< 1211200 1209600 >;
	};

	bwmon_llcc: qcom,bwmon-llcc@240B7300 {
		compatible = "qcom,bwmon4";
		reg = <0x240B7400 0x300>, <0x240B7300 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
		qcom,second-vote = <&qcom_llcc_l3_vote>;
	};

	bwmon_ddr: qcom,bwmon-ddr@24091000 {
		compatible = "qcom,bwmon5";
		reg = <0x24091000 0x1000>;
		reg-names = "base";
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
	};

	qcom-mpam-msc {
		compatible = "qcom,mpam-msc";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		qcom-slc-mpam@17D2EC00 {
			compatible = "qcom,slc-mpam";
			reg = <0x17D2EC00 0x400>;
			reg-names = "mon-base";
			qcom,msc-id = <2>;
			qcom,msc-name = "slc";
			qcom,dev-index = <0>;
			qcom,num-read-miss-cfg = <2>;
			qcom,num-cap-cfg = <5>;
			qcom,slc-clients = "APPS_CLIENT", "GPU_CLIENT",
				"NSP_CLIENT";
		};
	};

	qcom_slc_mpam: qcom,slc_mpam {
		compatible = "qcom,mpam-slc";
		qcom,msc-name = "slc";

		apps {
			qcom,client-id = <0>;
			qcom,client-name = "apps";

			part-id0 {
				qcom,part-id = <0>;
			};

			part-id1 {
				qcom,part-id = <1>;
			};

			part-id2 {
				qcom,part-id = <2>;
			};
		};

		gpu {
			qcom,client-id = <1>;
			qcom,client-name = "gpu";
		};

		nsp {
			qcom,client-id = <2>;
			qcom,client-name = "nsp";
		};
	};
};

#include "tuna-gdsc.dtsi"
#include "ipcc-test-no-slpi.dtsi"

&cam_cc_ipe_0_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_ofe_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_tfe_0_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_tfe_1_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_tfe_2_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_titan_top_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	compatible = "qcom,gdsc";
	interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
	interconnect-names = "mmnoc";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&disp_cc_mdss_core_gdsc {
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	parent-supply = <&VDD_MM_LEVEL>;
};

&disp_cc_mdss_core_int2_gdsc {
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	parent-supply = <&VDD_MM_LEVEL>;
};

&eva_cc_mvs0_gdsc {
	clocks = <&gcc GCC_EVA_AHB_CLK>;
	clock-names = "ahb_clk";
	status = "ok";
};

&eva_cc_mvs0c_gdsc {
	clocks = <&gcc GCC_EVA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&gcc_pcie_0_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_pcie_0_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_MX_LEVEL>;
	status = "ok";
};

&gcc_ufs_mem_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_MX_LEVEL>;
	status = "ok";
};

&gcc_ufs_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_usb30_prim_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_usb3_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_MX_LEVEL>;
	status = "ok";
};

&gpu_cc_cx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	parent-supply = <&VDD_CX_LEVEL>;
};

&gx_clkctl_gx_gdsc {
	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
};

&video_cc_mvs0_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
};

&video_cc_mvs0c_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
};

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	vm_comm_mem: vm_comm_mem_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x800000>;
	};

	adsp_mem_heap: adsp_heap_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0xC00000>;
	};

	cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x4800000>;
	};

	non_secure_display_memory: non_secure_display_region {
		compatible = "shared-dma-pool";
		reusable;
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		size = <0x0 0xc800000>;
		alignment = <0x0 0x400000>;
	};

	qseecom_mem: qseecom_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1400000>;
	};

	qseecom_ta_mem: qseecom_ta_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1400000>;
	};
};

#include "tuna-coresight.dtsi"
#include "tuna-debug.dtsi"
#include "tuna-pinctrl.dtsi"
#include "tuna-regulators.dtsi"
#include "tuna-usb.dtsi"
#include "tuna-qupv3.dtsi"
#include "msm-rdbg.dtsi"
#include "tuna-pmic-overlay.dtsi"
#include "tuna-walt.dtsi"
#include "tuna-thermal.dtsi"

&qupv3_se7_2uart {
	status = "ok";
};

&qupv3_se3_i2c {
	status = "ok";
	wcd_usbss: wcd939x_i2c@e {
		compatible = "qcom,wcd939x-i2c";
		reg = <0xe>;
		vdd-usb-cp-supply = <&L7B>;
	};
};