// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include "sun-pmic-overlay.dtsi"

&reserved_memory {
	spintable: spintable_region@90000000 {
		no-map;
		reg = <0x0 0x90000000 0x0 0x100000>;
	};
};

&MEDIUM_OFF_C4 {
	status = "nok";
};

&LARGE_OFF_C4 {
	status = "nok";
};

&MEDIUM_CLUSTER_PWR_DN {
	status = "nok";
};

&LARGE_CLUSTER_PWR_DN {
	status = "nok";
};

&APSS_OFF {
	status = "nok";
};

&arch_timer {
	clock-frequency = <500000>;
};

&memtimer {
	clock-frequency = <500000>;
};

&qupv3_se7_2uart {
	qcom,rumi_platform;
};

&tsens0 {
	status = "disabled";
};

&tsens1 {
	status = "disabled";
};

&tsens2 {
	status = "disabled";
};

&tsens3 {
	status = "disabled";
};

&soc {
	usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
	};

	usb_emuphy: phy@a784000 {
		compatible = "qcom,usb-emu-phy";
		reg = <0x0a784000 0x9500>;

		qcom,emu-init-seq = <0xfffff 0x4
			0xffff0 0x4
			0x100000 0x20
			0x0 0x20
			0x000101F0 0x20
			0x00100000 0x3c
			0x0 0x3c
			0x0 0x4>;
	};

	pcie0: qcom,pcie@1c00000 {
		reg = <0x01c00000 0x3000>,
			<0x01c06000 0x2000>,
			<0x40000000 0xf1d>,
			<0x40000f20 0xa8>,
			<0x40001000 0x1000>,
			<0x40100000 0x100000>,
			<0x01D07000 0x7000>,
			<0x01c05000 0x1000>;
		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
			"pcie_sm", "rumi";
		linux,pci-domain = <0>;
		qcom,target-link-speed = <0x1>;
		qcom,link-check-max-count = <200>; /* 1 sec */
		qcom,no-l0s-supported;
		qcom,no-l1-supported;
		qcom,no-l1ss-supported;
		qcom,no-aux-clk-sync;
		/*
		 * Comment out ICC and SMMU properties in main PCIe node
		 * if any issue in PCIe probe in RUMI
		 */
		status = "ok";
	};
};

&usb0 {
	dwc3@a600000 {
		usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
		dr_mode = "peripheral";
		maximum-speed = "high-speed";
	};
};

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qrbtc-sdm845";

	/* VDDA_UFS_CORE */
	vdda-phy-supply = <&pm_v6j_l1>;
	vdda-phy-max-microamp = <213000>;
	/*
	 * Platforms supporting Gear 5 && Rate B require a different
	 * voltage supply. Check the Power Grid document.
	 */
	vdda-phy-min-microvolt = <912000>;

	/* VDDA_UFS_0_1P2 */
	vdda-pll-supply = <&pm_v8g_l3>;
	vdda-pll-max-microamp = <18300>;

	/* Phy GDSC for VDD_MX, always on */
	vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;

	/* Qref power supply, Refer Qref diagram */
	vdda-qref-supply = <&pm_v8i_l3>;
	vdda-qref-max-microamp = <64500>;

	status = "ok";
};

&ufshc_mem {
	limit-tx-hs-gear = <1>;
	limit-rx-hs-gear = <1>;
	limit-rate = <2>; /* HS Rate-B */
	rpm-level = <0>;
	spm-level = <0>;

	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;

	vcc-supply = <&pm_humu_l17>;
	vcc-max-microamp = <1300000>;

	vccq-supply = <&pm_v8d_l1>;
	vccq-max-microamp = <1200000>;

	/* UFS Rst pin is always on. It is shared with VDD_PX14 */
	qcom,vddp-ref-clk-supply = <&pm_v8i_l2>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,vccq-parent-supply = <&pm_v8i_s7>;
	qcom,vccq-parent-max-microamp = <210000>;

	reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>;
	resets = <&gcc GCC_UFS_PHY_BCR>;
	reset-names = "rst";

	clock-names =
		"core_clk",
		"bus_aggr_clk",
		"iface_clk",
		"core_clk_unipro",
		"core_clk_ice",
		"ref_clk",
		"tx_lane0_sync_clk",
		"rx_lane0_sync_clk",
		"rx_lane1_sync_clk";
	clocks =
		<&gcc GCC_UFS_PHY_AXI_CLK>,
		<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
		<&gcc GCC_UFS_PHY_AHB_CLK>,
		<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
		<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
		<&rpmhcc RPMH_CXO_CLK>,
		<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
		<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
		<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

	qcom,disable-lpm;

	status = "ok";
};

&sdhc_2 {
	status = "ok";
	vdd-supply = <&pm_humu_l9>;
	qcom,vdd-voltage-level = <2950000 2960000>;
	qcom,vdd-current-level = <0 800000>;

	vdd-io-supply = <&pm_humu_l8>;
	qcom,vdd-io-voltage-level = <1800000 2960000>;
	qcom,vdd-io-current-level = <0 22000>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_on>;
	pinctrl-1 = <&sdc2_off>;

	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;

	resets = <&gcc GCC_SDCC2_BCR>;
	reset-names = "core_reset";

	is_rumi;
};

&VDD_MMCX_LEVEL {
	regulator-always-on;
};

&VDD_MXC_LEVEL {
	regulator-always-on;
	regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};

&bwmon_llcc_gold {
	qcom,hw-timer-hz = <192000>;
};

&bwmon_llcc_prime {
	qcom,hw-timer-hz = <192000>;
};