// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>

#include "sun-pmic-overlay.dtsi"

&soc {
	gpio_keys {
		compatible = "gpio-keys";
		label = "gpio-keys";

		pinctrl-names = "default";
		pinctrl-0 = <&key_vol_up_default>;

		vol_up {
			label = "volume_up";
			gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
			linux,input-type = <1>;
			linux,code = <KEY_VOLUMEUP>;
			gpio-key,wakeup;
			debounce,interval = <15>;
			linux,can-disable;
		};
	};
};

&regulator_ocp_notifier {
	periph-1c1-supply = <&L1B>;
	periph-1c2-supply = <&L2B>;
	periph-1c4-supply = <&L4B>;
	periph-1c5-supply = <&L5B>;
	periph-1c6-supply = <&L6B>;
	periph-1c7-supply = <&L7B>;
	periph-1c8-supply = <&L8B>;
	periph-1c9-supply = <&L9B>;
	periph-1ca-supply = <&L10B>;
	periph-1cb-supply = <&L11B>;
	periph-1cc-supply = <&L12B>;
	periph-1cd-supply = <&L13B>;
	periph-1ce-supply = <&L14B>;
	periph-1cf-supply = <&L15B>;
	periph-1d0-supply = <&L16B>;
	periph-1d1-supply = <&L17B>;
	periph-1e4-supply = <&BOB1>;
	periph-1e6-supply = <&BOB2>;
	periph-39b-supply = <&S1D>;
	periph-39e-supply = <&S2D_LEVEL>;
	periph-3a1-supply = <&S3D>;
	periph-3a4-supply = <&S4D>;
	periph-3a7-supply = <&S5D_LEVEL>;
	periph-3c1-supply = <&L1D>;
	periph-3c2-supply = <&L2D>;
	periph-3c3-supply = <&L3D>;
	periph-5aa-supply = <&S6F_LEVEL>;
	periph-5c1-supply = <&L1F>;
	periph-5c2-supply = <&L2F>;
	periph-5c3-supply = <&L3F>;
	periph-69b-supply = <&S1G>;
	periph-69e-supply = <&S2G_LEVEL>;
	periph-6a1-supply = <&S3G>;
	periph-6a4-supply = <&S4G>;
	periph-6a7-supply = <&S5G_LEVEL>;
	periph-6ad-supply = <&S7G_LEVEL>;
	periph-6c1-supply = <&L1G>;
	periph-6c2-supply = <&L2G>;
	periph-6c3-supply = <&L3G>;
	periph-89b-supply = <&S1I_LEVEL>;
	periph-8a1-supply = <&S3I_LEVEL>;
	periph-8a7-supply = <&S5I_LEVEL>;
	periph-8aa-supply = <&S6I_LEVEL>;
	periph-8ad-supply = <&S7I>;
	periph-8b0-supply = <&S8I>;
	periph-8c1-supply = <&L1I>;
	periph-8c2-supply = <&L2I>;
	periph-8c3-supply = <&L3I>;
	periph-99b-supply = <&S1J_LEVEL>;
	periph-99e-supply = <&S2J>;
	periph-9a1-supply = <&S3J>;
	periph-9a4-supply = <&S4J>;
	periph-9c1-supply = <&L1J>;
	periph-9c2-supply = <&L2J>;
	periph-9c3-supply = <&L3J_LEVEL>;
	periph-ac1-supply = <&L1K>;
	periph-ac2-supply = <&L2K>;
	periph-ac3-supply = <&L3K>;
	periph-ac4-supply = <&L4K>;
	periph-ac5-supply = <&L5K>;
	periph-ac6-supply = <&L6K>;
	periph-ac7-supply = <&L7K>;
	periph-c40-supply = <&L1M>;
	periph-c41-supply = <&L2M>;
	periph-c42-supply = <&L3M>;
	periph-c43-supply = <&L4M>;
	periph-c44-supply = <&L5M>;
	periph-c45-supply = <&L6M>;
	periph-c46-supply = <&L7M>;
	periph-d40-supply = <&L1N>;
	periph-d41-supply = <&L2N>;
	periph-d42-supply = <&L3N>;
	periph-d43-supply = <&L4N>;
	periph-d44-supply = <&L5N>;
	periph-d45-supply = <&L6N>;
	periph-d46-supply = <&L7N>;
};

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qmp-v4-sun";

	/* VDDA_UFS_CORE */
	vdda-phy-supply = <&pm_v6j_l1>;
	vdda-phy-max-microamp = <213000>;
	/*
	 * Platforms supporting Gear 5 && Rate B require a different
	 * voltage supply. Check the Power Grid document.
	 */
	vdda-phy-min-microvolt = <912000>;

	/* VDDA_UFS_0_1P2 */
	vdda-pll-supply = <&pm_v8g_l3>;
	vdda-pll-max-microamp = <18300>;

	/* Phy GDSC for VDD_MX, always on */
	vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;

	/* Qref power supply, Refer Qref diagram */
	vdda-qref-supply = <&pm_v8i_l3>;
	vdda-qref-max-microamp = <64500>;

	status = "ok";
};

&ufshc_mem {
	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;

	vcc-supply = <&pm_humu_l17>;
	vcc-max-microamp = <1300000>;

	vccq-supply = <&pm_v8d_l1>;
	vccq-max-microamp = <1200000>;

	/* UFS Rst pin is always on. It is shared with VDD_PX14 */
	qcom,vddp-ref-clk-supply = <&pm_v8i_l2>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,vccq-parent-supply = <&pm_v8i_s7>;
	qcom,vccq-parent-max-microamp = <210000>;

	reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>;
	resets = <&gcc GCC_UFS_PHY_BCR>;
	reset-names = "rst";

	status = "ok";
};

&sdhc_2 {
	status = "ok";
	vdd-supply = <&pm_humu_l9>;
	qcom,vdd-voltage-level = <2950000 2960000>;
	qcom,vdd-current-level = <0 800000>;

	vdd-io-supply = <&pm_humu_l8>;
	qcom,vdd-io-voltage-level = <1800000 2960000>;
	qcom,vdd-io-current-level = <0 5600>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_on>;
	pinctrl-1 = <&sdc2_off>;

	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;

	resets = <&gcc GCC_SDCC2_BCR>;
	reset-names = "core_reset";
};