// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	qcom,msm-id = <618 0x10000>;
	interrupt-parent = <&vgic>;

	chosen {
		bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		CPU0: cpu@0 {
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			cpu-idle-states = <&CPU_PWR_DWN
					   &CLUSTER_PWR_DWN>;
		};

		CPU1: cpu@100 {
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			cpu-idle-states = <&CPU_PWR_DWN
					   &CLUSTER_PWR_DWN>;

		};
	};

	idle-states {
		CPU_PWR_DWN: c4 {  /* Using Gold C4 latencies */
			compatible = "arm,idle-state";
			status = "disabled";
		};

		CLUSTER_PWR_DWN: d4 { /* C4+D4 */
			compatible = "arm,idle-state";
			status = "disabled";
		};
	};

	qcom,vm-config {
		compatible = "qcom,vm-1.0";
		vm-type = "aarch64-guest";
		boot-config = "fdt,unified";
		os-type = "linux";
		kernel-entry-segment = "kernel";
		kernel-entry-offset = <0x0 0x0>;
		vendor = "QTI";
		image-name = "qcom,trustedvm";
		qcom,pasid = <0x0 0x1c>;
		qcom,qtee-config-info = "p=3,9,39,77,78,7C,8F,97,C8,FE,11B,159,199,47E,7F1,CDF;";
		qcom,secdomain-ids = <45>;
		qcom,primary-vm-index = <0>;
		vm-uri = "vmuid/trusted-ui";
		vm-guid = "598085da-c516-5b25-a9c1-927a02819770";

		vm-attrs = "crash-fatal", "context-dump";

		memory {
			#address-cells = <0x2>;
			#size-cells = <0x0>;
			/*
			 * IPA address linux image is loaded at. Must be within
			 * first 1GB due to memory hotplug requirement.
			 */
			base-address = <0x0 0x88800000 >;
		};

		segments {
			config_cpio = <2>;
		};

		vcpus {
			config = "/cpus";
			affinity = "proxy";
			affinity-map = <0x5 0x6>;
			sched-priority = <0>;       /* relative to PVM */
			sched-timeslice = <2000>;   /* in ms */
		};

		interrupts {
			config = &vgic;
		};

		vdevices {
			generate = "/hypervisor";

			rm-rpc {
				vdevice-type = "rm-rpc";
				generate = "/hypervisor/qcom,resource-mgr";
				console-dev;
				message-size = <0x000000f0>;
				queue-depth = <0x00000008>;
				qcom,label = <0x1>;
			};

			virtio-mmio@0 {
				vdevice-type = "virtio-mmio";
				generate = "/virtio-mmio";
				peer-default;
				vqs-num = <0x1>;
				push-compatible = "virtio,mmio";
				dma-coherent;
				dma_base = <0x0 0x0>;
				memory {
					qcom,label = <0x11>;			//for persist.img
					#address-cells = <0x2>;
					base = <0x0 0xDA6F8000>;
				};
			};

			virtio-mmio@1 {
				vdevice-type = "virtio-mmio";
				generate = "/virtio-mmio";
				peer-default;
				vqs-num = <0x2>;
				push-compatible = "virtio,mmio";
				dma-coherent;
				dma_base = <0x0 0x4000>;
				memory {
					qcom,label = <0x10>;			//for system.img
					#address-cells = <0x2>;
					base = <0x0 0xDA6FC000>;
				};
			};

			swiotlb-shm {
				vdevice-type = "shm";
				generate = "/swiotlb";
				push-compatible = "swiotlb";
				peer-default;
				dma_base = <0x0 0x8000>;
				memory {
					qcom,label = <0x12>;
					#address-cells = <0x2>;
					base = <0x0 0xDA700000>;
				};
			};

		};
	};

	firmware: firmware {
		scm {
			compatible = "qcom,scm";
		};
	};

	soc: soc { };
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	vm_tlmm_irq: vm-tlmm-irq@0 {
		compatible = "qcom,tlmm-vm-irq";
		reg = <0x0 0x0>;
		interrupt-controller;
		#interrupt-cells = <2>;
		status="disabled";
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,sun-vm-pinctrl";
		reg = <0x0F000000 0x1000000>;
		interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		/* Valid pins */
		gpios = /bits/ 16 <86 87 133 137 48 49 50 51 161 162 91 60 61 62 63 88>;
		status="disabled";
	};

	tlmm-vm-mem-access {
		compatible = "qcom,tlmm-vm-mem-access";
		tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 48 0
					&tlmm 49 0 &tlmm 50 0 &tlmm 51 0 &tlmm 161 0 &tlmm 162 0
					&tlmm 91 0 &tlmm 60 0 &tlmm 61 0 &tlmm 62 0 &tlmm 63 0
					&tlmm 88 0>;
		status="disabled";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	vgic: interrupt-controller@16000000 {
		compatible = "arm,gic-v3";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x16000000 0x10000>,     /* GICD */
		      <0x16080000 0x200000>;    /* GICR * 8 */
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		always-on;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};
};

#include "msm-arm-smmu-sun-vm.dtsi"
#include "sun-vm-dma-heaps.dtsi"