// SPDX-License-Identifier: BSD-3-Clause

/*
 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interconnect/qcom,alor.h>

&wlan_msa_mem {
	status = "disabled";
};

&wpss_mem {
	status = "disabled";
};

&wpss_pas {
	status = "disabled";
};

&pcie0 {
	status = "ok";
};

&tlmm {
	cnss_pins {
		cnss_wlan_en_active: cnss_wlan_en_active {
			mux {
				pins = "gpio16";
				function = "gpio";
			};

			config {
				pins = "gpio16";
				drive-strength = <16>;
				output-high;
				bias-pull-up;
			};
		};

		cnss_wlan_en_sleep: cnss_wlan_en_sleep {
			mux {
				pins = "gpio16";
				function = "gpio";
			};

			config {
				pins = "gpio16";
				drive-strength = <2>;
				output-low;
				bias-pull-down;
			};
		};

		cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
			mux {
				pins = "gpio18";
				function = "wcn_sw_ctrl";
			};
		};

		cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
			mux {
				pins = "gpio19";
				function = "wcn_sw";
			};
		};
	};
};

&reserved_memory {
	cnss_wlan_mem: cnss_wlan_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
	};
};

&soc {
	wlan_kiwi: qcom,cnss-kiwi@b0000000 {
		compatible = "qcom,cnss-kiwi";
		reg = <0x0 0xb0000000 0x0 0x10000>;
		reg-names = "smmu_iova_ipa";
		qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;

		supported-ids = <0x1107>;
		wlan-en-gpio = <&tlmm 16 0>;
		qcom,bt-en-gpio = <&pm8550ve_d_gpios 3 0>;
		qcom,sw-ctrl-gpio = <&tlmm 18 0>;
		/* List of GPIOs to be setup for interrupt wakeup capable */
		mpm_wake_set_gpios = <18 19>;
		pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
				"sw_ctrl_wl_cx";
		pinctrl-0 = <&cnss_wlan_en_active>;
		pinctrl-1 = <&cnss_wlan_en_sleep>;
		pinctrl-2 = <&cnss_wlan_sw_ctrl>;
		pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
		qcom,wlan;
		qcom,wlan-rc-num = <0>;
		qcom,wlan-ramdump-dynamic = <0x780000>;
		cnss-enable-self-recovery;
		qcom,wlan-cbc-enabled;
		use-pm-domain;
		qcom,same-dt-multi-dev;
		/* For AOP communication, use direct QMP instead of mailbox */
		qcom,qmp = <&aoss_qmp>;

		//TODO REGULATORS VOTING
		//TODO BUS-BW

		//TODO PMU-VREG-PDC mapping for ol_cpr
		//TODO PDC AOP cmd for hmt

		/* cpu mask used for wlan tx rx interrupt affinity
		 * <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
		 */
		wlan-txrx-intr-cpumask = <0x3 0x30>;
	};
};

&pcie_rp {

	cnss_pci0: cnss_pci0 {
		reg = <0 0 0 0 0>;
		qcom,iommu-group = <&cnss_pci_iommu_group0>;
		memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;

		#address-cells = <2>;
		#size-cells = <2>;

		cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
			/* address-cells =3 size-cells=2 from alor-pcie.dtsi */
			iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
					  <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
			};

		cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
			qcom,iommu-msi-size = <0x1000>;
			qcom,iommu-geometry = <0x0 0x98000000 0x0 0x18010000>;
			qcom,iommu-dma = "fastmap";
			qcom,iommu-pagetable = "coherent";
			qcom,iommu-faults = "stall-disable", "HUPCF",
					    "non-fatal";
		};
	};
};