// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/clock/qcom,gpucc-kera.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-tuna.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

/ {
	model = "Qualcomm Technologies, Inc. Kera";
	compatible = "qcom,kera";
	qcom,msm-id = <659 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	memory {
		device_type = "memory";
		reg = <0 0 0 0>;
	};

	chosen: chosen {
		bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops";
		stdout-path = "/soc/qcom,qupv3_1_geni_se@8c0000/qcom,qup_uart@894000:115200n8";
	};

	reserved_memory: reserved-memory {};

	ddr-regions { };

	firmware: firmware {
		qcom_scm: qcom_scm { };
	};

	aliases {
		serial0 = &qupv3_se13_2uart;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_2>;
			L2_2: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_3>;
			L2_3: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_4>;
			L2_4: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_5>;
			L2_5: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_6>;
			L2_6: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_7>;
			L2_7: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU3>;
				};

				core1 {
					cpu = <&CPU4>;
				};

				core2 {
					cpu = <&CPU5>;
				};

				core3 {
					cpu = <&CPU6>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	soc: soc { };

	hypervisor: hypervisor {
		gh_watchdog: qcom,gh-watchdog { };
	};
};

&firmware {
	qcom_scm {
		compatible = "qcom,scm";
		qcom,dload-mode = <&tcsr 0x19000>;
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};
};

#include "kera-reserved-memory.dtsi"
#include "msm-arm-smmu-kera.dtsi"
#include "kera-dma-heaps.dtsi"

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* global autoconfigured region for contiguous allocations */
	system_cma: linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
		linux,cma-default;
	};

	kinfo_mem: debug_kinfo_region {
		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
		size = <0x0 0x1000>;
		no-map;
	};

	va_md_mem: va_md_mem_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		size = <0 0x1000000>;
	};

	ramoops_mem: ramoops-region {
		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
		size = <0x0 0x200000>;
		no-map;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,	/* GICD */
		      <0x17180000 0x200000>;	/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
			      <0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};

	qcom,secure-buffer {
		compatible = "qcom,secure-buffer";
		qcom,vmid-cp-camera-preview-ro;
	};

	apps_rsc: rsc@17a00000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x17a00000 0x10000>,
		      <0x17a10000 0x10000>,
		      <0x17a20000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		qcom,drv-count = <3>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

		apps_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0xd00>;
			qcom,tcs-distance = <0x2a0>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    3>,
						  <SLEEP_TCS     2>,
						  <WAKE_TCS      2>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 1>;
			};
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x1000>;
		reg-names = "drv-0";
		qcom,drv-count = <1>;
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;

		disp_rsc_drv0: drv@0 {
			qcom,drv-id = <0>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <SLEEP_TCS     1>,
						  <WAKE_TCS      1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,kera-pdc", "qcom,pdc";
		reg = <0xb220000 0x10000>, <0x17c000f0 0x60>;
		qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
				  <10 230 1>, <11 724 1>, <12 716 1>,
				  <13 727 1>, <14 720 1>, <15 726 1>,
				  <16 721 1>, <17 262 1>, <18 70 1>,
				  <19 723 1>, <20 234 1>, <22 725 1>,
				  <23 231 1>, <24 504 5>, <30 510 8>,
				  <40 520 6>, <51 531 4>, <58 538 2>,
				  <61 541 5>, <66 92 1>, <67 547 13>,
				  <80 240 1>, <81 235 1>, <82 310 2>,
				  <84 248 1>, <85 241 1>, <86 238 2>,
				  <88 254 1>, <89 509 1>, <90 563 1>,
				  <91 259 2>, <93 201 1>, <94 246 1>,
				  <95 93 1>, <96 611 29>, <125 63 1>,
				  <126 366 2>, <128 374 1>, <129 377 1>,
				  <130 428 1>, <131 434 2>, <133 437 1>,
				  <134 452 2>, <136 458 2>, <138 464 11>,
				  <149 671 1>, <150 688 1>, <151 714 2>,
				  <153 722 1>, <154 255 1>, <155 269 2>,
				  <157 276 1>, <158 287 1>, <159 306 4>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	adsp_pas: remoteproc-adsp@03000000 {
		compatible = "qcom,kera-adsp-pas";
		reg = <0x03000000 0x10000>;
		status = "ok";

		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;

		reg-names = "cx", "mx";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnect-names = "rproc_ddr", "crypto_ddr";

		firmware-name = "adsp.mdt", "adsp_dtb.mdt";
		memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>;

		/* Inputs from ssc */
		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					<&adsp_smp2p_in 0 0>,
					<&adsp_smp2p_in 2 0>,
					<&adsp_smp2p_in 1 0>,
					<&adsp_smp2p_in 3 0>,
					<&adsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to turing */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";
	};

	cdsp_pas: remoteproc-cdsp@32300000 {
		compatible = "qcom,kera-cdsp-pas";
		reg = <0x32300000 0x10000>;
		status = "ok";

		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		nsp-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		reg-names = "cx","mx","nsp";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnect-names = "rproc_ddr", "crypto_ddr";

		firmware-name = "cdsp.mdt", "cdsp_dtb.mdt";

		memory-region = <&cdsp_mem &q6_cdsp_dtb_mem &global_sync_mem>;

		/* Inputs from turing */
		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					<&cdsp_smp2p_in 0 0>,
					<&cdsp_smp2p_in 2 0>,
					<&cdsp_smp2p_in 1 0>,
					<&cdsp_smp2p_in 3 0>,
					<&cdsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";
	};

	modem_pas: remoteproc-mss@04080000 {
		compatible = "qcom,kera-modem-pas";
		reg = <0x4080000 0x10000>;
		status = "ok";

		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;

		reg-names = "cx", "mx";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnect-names = "rproc_ddr", "crypto_ddr";

		firmware-name = "modem.mdt", "modem_dtb.mdt";

		memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma &dsm_partition_1_mem &dsm_partition_2_mem>;

		/* Inputs from mss */
		interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
					<&modem_smp2p_in 0 0>,
					<&modem_smp2p_in 2 0>,
					<&modem_smp2p_in 1 0>,
					<&modem_smp2p_in 3 0>,
					<&modem_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to mss */
		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "stop";
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,kera-tlmm";
		reg = <0xf000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;
		qcom,gpios-reserved = <20 21 22 23 100 111 112 116>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	ipcc_mproc: qcom,ipcc@406000 {
		compatible = "qcom,ipcc";
		reg = <0x406000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	aoss_qmp: power-controller@c300000 {
		compatible = "qcom,aoss-qmp";
		reg = <0xc300000 0x400>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		#power-domain-cells = <1>;
		#clock-cells = <0>;
	};

	qmp_aop: qcom,qmp-aop {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	qmp_tme: qcom,qmp-tme {
		compatible = "qcom,qmp-mbox";
		qcom,remote-pid = <14>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		mbox-names = "tme_qmp";
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;

		label = "tme";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	cache-controller@24800000 {
		compatible = "qcom,kera-llcc";
		reg = <0x24800000 0x200000>, <0x24C00000 0x200000>,
			<0x26800000 0x200000>, <0x26C00000 0x200000>;
		reg-names = "llcc0_base", "llcc2_base",
			"llcc_broadcast_or_base", "llcc_broadcast_and_base";
		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		cap-based-alloc-and-pwr-collapse;
	};

	tcsr: syscon@1fc0000 {
		compatible = "syscon";
		reg = <0x1fc0000 0x30000>;
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};


	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_smem_mailbox_1_out: qcom,smp2p-smem-mailbox-1-out {
			qcom,entry-name = "smem-mailbox";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_smem_mailbox_1_in: qcom,smp2p-smem-mailbox-1-in {
			qcom,entry-name = "smem-mailbox";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-soccp {
		compatible = "qcom,smp2p";
		qcom,smem = <617>, <616>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <19>;

		soccp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		soccp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,msm-imem@14680000 {
		compatible = "qcom,msm-imem";
		reg = <0x14680000 0x1000>;
		ranges = <0x0 0x14680000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,pil-reloc-info";
			reg = <0x94c 0xc8>;
		};

		pil@6dc {
			compatible = "qcom,msm-imem-pil-disable-timeout";
			reg = <0x6dc 0x4>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};

		modem_dsm@c98 {
			compatible = "qcom,msm-imem-mss-dsm";
			reg = <0xc98 0x10>;
		};

		sys_dbg@af8 {
			compatible = "qcom,msm-imem-gpu-dump-skip";
			reg = <0xb0c 0x4>;
		};
	};

	eud: qcom,msm-eud@88e0000 {
		compatible = "qcom,msm-eud";
		interrupt-names = "eud_irq";
		interrupt-parent = <&pdc>;
		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x88e0000 0x2000>,
			<0x88e2000 0x1000>;
		reg-names = "eud_base", "eud_mode_mgr2";
		qcom,secure-eud-en;
		qcom,eud-utmi-delay = /bits/ 16 <255>;
		status = "ok";
	};

	google,debug-kinfo {
		compatible = "google,debug-kinfo";
		memory-region = <&kinfo_mem>;
	};

	mini_dump_node {
		compatible = "qcom,minidump";
		status = "ok";
	};

	va_mini_dump {
		compatible = "qcom,va-minidump";
		memory-region = <&va_md_mem>;
		status = "ok";
	};

	qcom_ramoops {
		compatible = "qcom,ramoops";
		memory-region = <&ramoops_mem>;
		pmsg-size = <0x200000>;
		mem-type = <2>;
	};

	qcom,mpm2-sleep-counter@c221000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem_heap>;
		restrict-access;
	};

	qfprom: qfprom@221c8000 {
		compatible = "qcom,kera-qfprom", "qcom,qfprom";
		reg = <0x221c8000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		read-only;
		ranges;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_1_pipe_clk: pcie_1_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_0_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_1_clk";
			#clock-cells = <0>;
		};

		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_tx_symbol_0_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	rpmhcc: clock-controller {
		compatible = "fixed-clock";
		clock-output-names = "rpmh_clocks";
		clock-frequency = <19200000>;
		#clock-cells = <1>;
	};

	cambistmclkcc: clock-controller@1760000 {
		compatible = "qcom,dummycc";
		clock-output-names = "cambistmclkcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,dummycc";
		clock-output-names = "camcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,dummycc";
		clock-output-names = "dispcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gpucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	tcsrcc: clock-controller@1f40000 {
		compatible = "qcom,dummycc";
		clock-output-names = "tcsrcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@aaf0000 {
		compatible = "qcom,dummycc";
		clock-output-names = "videocc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gh-secure-vm-loader@2 {
		compatible = "qcom,gh-secure-vm-loader";
		qcom,pas-id = <35>;
		qcom,vmid = <50>;
		qcom,firmware-name = "cpusys_vm";
		memory-region = <&cpusys_vm_mem>;
	};
};

#include "tuna-gdsc.dtsi"
#include "ipcc-test-no-slpi.dtsi"

&cam_cc_ipe_0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_ofe_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_tfe_0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_tfe_1_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_tfe_2_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_titan_top_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&disp_cc_mdss_core_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&disp_cc_mdss_core_int2_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_0_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_1_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_1_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_ufs_mem_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_ufs_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_usb30_prim_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_usb3_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gpu_cc_cx_gdsc_hw_ctrl {
	reg = <0x3d99124 0x4>;
};

&gpu_cc_cx_gdsc {
	compatible = "regulator-fixed";
	reg = <0x3d99110 0x4>;
	status = "ok";
};

&gpu_cc_gx_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&video_cc_mvs0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&video_cc_mvs0c_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
		compatible = "qcom,cmd-db";
		no-map;
		reg = <0x0 0x81c60000 0x0 0x20000>;
	};

	adsp_mem_heap: adsp_heap_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0xC00000>;
	};

	cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x4800000>;
	};
};

#include "kera-debug.dtsi"
#include "kera-coresight.dtsi"
#include "kera-pinctrl.dtsi"
#include "kera-stub-regulators.dtsi"
#include "kera-usb.dtsi"
#include "kera-qupv3.dtsi"

&qupv3_se13_2uart {
	status = "ok";
};