// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-sun.h>
#include <dt-bindings/clock/qcom,evacc-sun.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,gpucc-sun.h>
#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-sun.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sun.h>

/ {
	model = "Qualcomm Technologies, Inc. Sun";
	compatible = "qcom,sun";
	qcom,msm-id = <618 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;
	memory { device_type = "memory"; reg = <0 0 0 0>; };


	chosen: chosen {
		bootargs = "maxcpus=1 nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
		stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
	};

	aliases {
		serial0 = &qupv3_se7_2uart;
		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
	};

	firmware: firmware { };

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x400>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x500>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU6: cpu@10000 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x10000>;
			enable-method = "psci";
			next-level-cache = <&L2_6>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			};
		};

		CPU7: cpu@10100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x10100>;
			enable-method = "psci";
			next-level-cache = <&L2_6>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU6>;
				};

				core1 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	reserved_memory: reserved-memory { };

	soc: soc { };
};

&firmware {
	qcom-scm {
		compatible = "qcom,scm";
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	ipcc_mproc: qcom,ipcc@406000 {
		compatible = "qcom,ipcc";
		reg = <0x406000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr: syscon@1fc0000 {
		compatible = "syscon";
		reg = <0x1fc0000 0x30000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};


	tlmm: pinctrl@f000000 {
		compatible = "qcom,sun-tlmm";
		reg = <0xf000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	intc: interrupt-controller@16000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x16000000 0x10000>,	/* GICD */
		      <0x16080000 0x200000>;	/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	memtimer: timer@16800000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x16800000 0x1000>;
		clock-frequency = <19200000>;

		frame@16801000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x16801000 0x1000>,
			      <0x16802000 0x1000>;
		};

		frame@16803000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x16803000 0x1000>;
			status = "disabled";
		};

		frame@16805000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x16805000 0x1000>;
			status = "disabled";
		};

		frame@16807000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x16807000 0x1000>;
			status = "disabled";
		};

		frame@16809000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x16809000 0x1000>;
			status = "disabled";
		};

		frame@1680b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1680b000 0x1000>;
			status = "disabled";
		};

		frame@1680d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1680d000 0x1000>;
			status = "disabled";
		};
	};

	cache-controller@24800000 {
		compatible = "qcom,sun-llcc";
		reg = <0x24800000 0x2000000> , <0x26800000 0x200000>;
		reg-names = "llcc_base", "llcc_broadcast_base";
		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		cap-based-alloc-and-pwr-collapse;
	};


	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	qcom_tzlog: tz-log@0 {
	};

	clk_virt: interconnect@0 {
		compatible = "qcom,sun-clk_virt";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	mc_virt: interconnect@1 {
		compatible = "qcom,sun-mc_virt";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	config_noc: interconnect@1600000 {
		compatible = "qcom,sun-cnoc_cfg";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	cnoc_main: interconnect@1500000 {
		compatible = "qcom,sun-cnoc_main";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	system_noc: interconnect@1680000 {
		compatible = "qcom,sun-system_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	pcie_noc: interconnect@16c0000 {
		compatible = "qcom,sun-pcie_anoc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	aggre1_noc: interconnect@16e0000 {
		compatible = "qcom,sun-aggre1_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	aggre2_noc: interconnect@1700000 {
		compatible = "qcom,sun-aggre2_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	mmss_noc: interconnect@1780000 {
		compatible = "qcom,sun-mmss_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	gem_noc: interconnect@24100000 {
		compatible = "qcom,sun-gem_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	nsp_noc: interconnect@320c0000 {
		compatible = "qcom,sun-nsp_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	lpass_ag_noc: interconnect@7e40000 {
		compatible = "qcom,sun-lpass_ag_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	lpass_lpiaon_noc: interconnect@7400000 {
		compatible = "qcom,sun-lpass_lpiaon_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	lpass_lpicx_noc: interconnect@7420000 {
		compatible = "qcom,sun-lpass_lpicx_noc";
		qcom,stub;
		#interconnect-cells = <1>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_0_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_1_clk";
			#clock-cells = <0>;
		};

		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_tx_symbol_0_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	cxo: bi_tcxo {
		compatible = "fixed-factor-clock";
		clocks = <&xo_board>;
		clock-mult = <1>;
		clock-div = <4>;
		#clock-cells = <0>;
		clock-output-names = "bi_tcxo";
	};

	cxo_a: bi_tcxo_ao {
		compatible = "fixed-factor-clock";
		clocks = <&xo_board>;
		clock-mult = <1>;
		clock-div = <4>;
		#clock-cells = <0>;
		clock-output-names = "bi_tcxo_ao";
	};

	rpmhcc: clock-controller {
		compatible = "fixed-clock";
		clock-output-names = "rpmh_clocks";
		clock-frequency = <19200000>;
		#clock-cells = <1>;
	};

	cambistmclkcc: clock-controller@1760000 {
		compatible = "qcom,dummycc";
		clock-output-names = "cambistmclkcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,sun-camcc", "syscon";
		reg = <0xade0000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&sleep_clk>,
			 <&gcc GCC_CAMERA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "sleep_clk",
			      "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,dummycc";
		clock-output-names = "dispcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	evacc: clock-controller@abf0000 {
		compatible = "qcom,sun-evacc", "syscon";
		reg = <0xabf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&sleep_clk>,
			 <&gcc GCC_EVA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "sleep_clk",
			      "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,sun-gcc", "syscon";
		reg = <0x100000 0x1f4200>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&pcie_0_pipe_clk>,
			 <&sleep_clk>,
			 <&ufs_phy_rx_symbol_0_clk>,
			 <&ufs_phy_rx_symbol_1_clk>,
			 <&ufs_phy_tx_symbol_0_clk>,
			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
		clock-names = "bi_tcxo",
			      "pcie_0_pipe_clk",
			      "sleep_clk",
			      "ufs_phy_rx_symbol_0_clk",
			      "ufs_phy_rx_symbol_1_clk",
			      "ufs_phy_tx_symbol_0_clk",
			      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gpucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gxclkctl: clock-controller@3d64000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gxclkctl_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	tcsrcc: clock-controller@f100000 {
		compatible = "qcom,dummycc";
		clock-output-names = "tcsrcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@aaf0000 {
		compatible = "qcom,dummycc";
		clock-output-names = "videocc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	apsscc: syscon@16450000 {
		compatible = "syscon";
		reg = <0x16450000 0x3553000>;
	};

	mccc: syscon@240ba000 {
		compatible = "syscon";
		reg = <0x240ba000 0x800>;
	};

	/* CAM_CC GDSCs */
	cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c {
		compatible = "qcom,gdsc";
		reg = <0xadf017c 0x4>;
		regulator-name = "cam_cc_ipe_0_gdsc";
		parent-supply = <&cam_cc_titan_top_gdsc>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
		qcom,support-cfg-gdscr;
	};

	cam_cc_ofe_gdsc: qcom,gdsc@adf00c8 {
		compatible = "qcom,gdsc";
		reg = <0xadf00c8 0x4>;
		regulator-name = "cam_cc_ofe_gdsc";
		parent-supply = <&cam_cc_titan_top_gdsc>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
		qcom,support-cfg-gdscr;
	};

	cam_cc_tfe_0_gdsc: qcom,gdsc@adf1004 {
		compatible = "qcom,gdsc";
		reg = <0xadf1004 0x4>;
		regulator-name = "cam_cc_tfe_0_gdsc";
		parent-supply = <&cam_cc_titan_top_gdsc>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	cam_cc_tfe_1_gdsc: qcom,gdsc@adf1084 {
		compatible = "qcom,gdsc";
		reg = <0xadf1084 0x4>;
		regulator-name = "cam_cc_tfe_1_gdsc";
		parent-supply = <&cam_cc_titan_top_gdsc>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	cam_cc_tfe_2_gdsc: qcom,gdsc@adf10ec {
		compatible = "qcom,gdsc";
		reg = <0xadf10ec 0x4>;
		regulator-name = "cam_cc_tfe_2_gdsc";
		parent-supply = <&cam_cc_titan_top_gdsc>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	cam_cc_titan_top_gdsc: qcom,gdsc@adf134c {
		compatible = "qcom,gdsc";
		reg = <0xadf134c 0x4>;
		regulator-name = "cam_cc_titan_top_gdsc";
		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	/* DISP_CC GDSCs */
	disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
		compatible = "qcom,stub-regulator";
		regulator-name = "disp_cc_mdss_core_gdsc";
		qcom,support-hw-trigger;
	};

	disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
		compatible = "qcom,stub-regulator";
		regulator-name = "disp_cc_mdss_core_int2_gdsc";
		qcom,support-hw-trigger;
	};

	/* EVA_CC GDSCs */
	eva_cc_mvs0_gdsc: qcom,gdsc@abf8068 {
		compatible = "qcom,gdsc";
		reg = <0xabf8068 0x4>;
		regulator-name = "eva_cc_mvs0_gdsc";
		parent-supply = <&eva_cc_mvs0c_gdsc>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
		qcom,support-cfg-gdscr;
	};

	eva_cc_mvs0c_gdsc: qcom,gdsc@abf8034 {
		compatible = "qcom,gdsc";
		reg = <0xabf8034 0x4>;
		regulator-name = "eva_cc_mvs0c_gdsc";
		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	gcc_apcs_gdsc_vote_ctrl: syscon@15214c {
		compatible = "syscon";
		reg = <0x15214c 0x4>;
	};

	/* GCC GDSCs */
	gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
		compatible = "qcom,gdsc";
		reg = <0x16b004 0x4>;
		regulator-name = "gcc_pcie_0_gdsc";
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,retain-regs;
		qcom,no-status-check-on-disable;
		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
		qcom,support-cfg-gdscr;
	};

	gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
		compatible = "qcom,gdsc";
		reg = <0x16c000 0x4>;
		regulator-name = "gcc_pcie_0_phy_gdsc";
		parent-supply = <&VDD_MX_LEVEL>;
		qcom,retain-regs;
		qcom,no-status-check-on-disable;
		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
		qcom,support-cfg-gdscr;
	};

	gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
		compatible = "qcom,gdsc";
		reg = <0x19e000 0x4>;
		regulator-name = "gcc_ufs_mem_phy_gdsc";
		parent-supply = <&VDD_MX_LEVEL>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
		compatible = "qcom,gdsc";
		reg = <0x177004 0x4>;
		regulator-name = "gcc_ufs_phy_gdsc";
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
		compatible = "qcom,gdsc";
		reg = <0x139004 0x4>;
		regulator-name = "gcc_usb30_prim_gdsc";
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
		compatible = "qcom,gdsc";
		reg = <0x150018 0x4>;
		regulator-name = "gcc_usb3_phy_gdsc";
		parent-supply = <&VDD_MX_LEVEL>;
		qcom,retain-regs;
		qcom,support-cfg-gdscr;
	};

	/* GPU_CC GDSCs */
	gpu_cc_cx_gdsc_hw_ctrl: syscon@3d99094 {
		compatible = "syscon";
		reg = <0x3d99094 0x4>;
	};

	gpu_cc_cx_gdsc: qcom,gdsc@3d99080 {
		compatible = "qcom,stub-regulator";
		regulator-name = "gpu_cc_cx_gdsc";
	};

	/* GX_CLKCTL GDSCs */
	gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 {
		compatible = "qcom,stub-regulator";
		regulator-name = "gx_clkctl_gx_gdsc";
	};

	/* VIDEO_CC GDSCs */
	video_cc_mvs0_gdsc: qcom,gdsc@aaf8068 {
		compatible = "qcom,stub-regulator";
		regulator-name = "video_cc_mvs0_gdsc";
		qcom,support-hw-trigger;
	};

	video_cc_mvs0c_gdsc: qcom,gdsc@aaf8034 {
		compatible = "qcom,stub-regulator";
		regulator-name = "video_cc_mvs0c_gdsc";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	ufsphy_mem: ufsphy_mem@1d80000 {
		reg = <0x1d80000 0x2000>;
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;
		clock-names = "ref_clk_src",
			"ref_aux_clk", "qref_clk",
			"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
			"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
		clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
			<&tcsrcc TCSR_UFS_CLKREF_EN>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>;
		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	ice_cfg: shared_ice {
		 alg1 {
		      alg-name = "alg1";
		      rx-alloc-percent = <60>;
		      status = "disabled";
		 };

		 alg2 {
		      alg-name = "alg2";
		      status = "disabled";

		 };

		 alg3 {
		      alg-name = "alg3";
		      num-core = <28 28 15 13>;
		      status = "ok";
		 };
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>,
		      <0x1d88000 0x8000>,
		      <0x1d90000 0x9800>;
		reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */
		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_LN_BB_CLK3>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<100000000 403000000>,
			<0 0>,
			<0 0>,
			<100000000 403000000>,
			<100000000 403000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		qcom,ufs-bus-bw,name = "ufshc_mem";
		qcom,ufs-bus-bw,num-cases = <30>;
		qcom,ufs-bus-bw,num-paths = <2>;
		qcom,ufs-bus-bw,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<0 0>, <0 0>,          /* No vote */
		<922 0>, <1000 0>,     /* PWM G1 */
		<1844 0>, <1000 0>,    /* PWM G2 */
		<3688 0>, <1000 0>,    /* PWM G3 */
		<7376 0>, <1000 0>,    /* PWM G4 */
		<14752 0>, <1000 0>,   /* PWM G5 */
		<1844 0>, <1000 0>,    /* PWM G1 L2 */
		<3688 0>, <1000 0>,    /* PWM G2 L2 */
		<7376 0>, <1000 0>,    /* PWM G3 L2 */
		<14752 0>, <1000 0>,   /* PWM G4 L2 */
		<29504 0>, <1000 0>,   /* PWM G5 L2 */
		<127796 0>, <1000 0>,  /* HS G1 RA */
		<255591 0>, <1000 0>,  /* HS G2 RA */
		<1492582 0>, <102400 0>,  /* HS G3 RA */
		<2915200 0>, <204800 0>,  /* HS G4 RA */
		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
		<149422 0>, <1000 0>,  /* HS G1 RB */
		<298189 0>, <1000 0>,  /* HS G2 RB */
		<1492582 0>, <102400 0>,  /* HS G3 RB */
		<2915200 0>, <204800 0>,  /* HS G4 RB */
		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
		/* As UFS working in HS G3 RB L2 mode, aggregated
		 * bandwidth (AB) should take care of providing
		 * optimum throughput requested. However, as tested,
		 * in order to scale up CNOC clock, instantaneous
		 * bindwidth (IB) needs to be given a proper value too.
		 */
		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
		<5836800 0>, <819200 0>,      /* HS G5 RA L2*/
		<5836800 0>, <819200 0>,      /* HS G5 RB L2 */
		<7643136 0>, <819200 0>;      /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
		"HS_RA_G5_L2", "HS_RB_G5_L2",
		"MAX";

		iommus = <&apps_smmu 0x60 0x0>;
		shared-ice-cfg = <&ice_cfg>;

		qcom,bypass-pbl-rst-wa;

		status = "disabled";

		qos0 {
			mask = <0xfc>;
			vote = <44>;
			perf;
			cpu_freq_vote = <2 5 7>;
		};

		qos1 {
			mask = <0x03>;
			vote = <44>;
			cpu_freq_vote = <0>;
		};
	};
};

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gunyah_hyp_mem: gunyah_hyp_region@80000000 {
		no-map;
		reg = <0x0 0x80000000 0x0 0xe00000>;
	};

	cpusys_vm_mem: cpusys_vm_region@80e00000 {
		no-map;
		reg = <0x0 0x80e00000 0x0 0x400000>;
	};

	cpucp_mem: cpucp_region@81200000 {
		no-map;
		reg = <0x0 0x81200000 0x0 0x200000>;
	};

	/*
	 * hyp_tags_mem is dynamically removed from the RAM
	 * partition tables before boot occurs. Size of region
	 * varies.
	 */

	/* merged xbl_dtlog, xbl_ramdump and aop_image regions */
	xbl_aop_merged_mem: xbl_aop_merged_region@81a00000 {
		no-map;
		reg = <0x0 0x81a00000 0x0 0x260000>;
	};

	aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
		compatible = "qcom,cmd-db";
		no-map;
		reg = <0x0 0x81c60000 0x0 0x20000>;
	};

	/* merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
	aop_tme_uefi_merged_mem: aop_tme_uefi_merged_region@81c80000 {
		no-map;
		reg = <0x0 0x81c80000 0x0 0x74000>;
	};

	/* secdata region can be reused by apps */

	smem_mem: smem_region@81d00000 {
		no-map;
		reg = <0x0 0x81d00000 0x0 0x200000>;
	};

	pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 {
		no-map;
		reg = <0x0 0x81f00000 0x0 0x100000>;
	};

	cpucp_scandump_mem: cpucp_scandump_region@82000000 {
		no-map;
		reg = <0x0 0x82000000 0x0 0x380000>;
	};

	adsp_mhi_mem: adsp_mhi_region@82380000 {
		no-map;
		reg = <0x0 0x82380000 0x0 0x20000>;
	};

	soccp_sdi_mem: soccp_sdi_region@823a0000 {
		no-map;
		reg = <0x0 0x823a0000 0x0 0x40000>;
	};

	pmic_minii_dump_mem: pmic_minii_dump_region@823e0000 {
		no-map;
		reg = <0x0 0x823e0000 0x0 0x80000>;
	};

	pvm_fw_mem: pvm_fw_region@824a0000 {
		no-map;
		reg = <0x0 0x824a0000 0x0 0x100000>;
	};

	/* hyp_mem_database_mem is removed by HYP in the RAM partition table */

	global_sync_mem: global_sync_region@82600000 {
		no-map;
		reg = <0x0 0x82600000 0x0 0x100000>;
	};

	tz_stat_mem: tz_stat_region@82700000 {
		no-map;
		reg = <0x0 0x82700000 0x0 0x100000>;
	};

	qdss_apps_mem: qdss_apps_region@82800000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0x82800000 0x0 0x2000000>;
		reusable;
	};

	dsm_partition_1_mem: dsm_partition_1_region@86b00000 {
		no-map;
		reg = <0x0 0x86b00000 0x0 0x4900000>;
	};

	dsm_partition_2_mem: dsm_partition_2_region@8b400000 {
		no-map;
		reg = <0x0 0x8b400000 0x0 0x800000>;
	};

	mpss_mem: mpss_region@8bc00000 {
		no-map;
		reg = <0x0 0x8bc00000 0x0 0xf400000>;
	};

	q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 {
		no-map;
		reg = <0x0 0x9b000000 0x0 0x80000>;
	};

	ipa_fw_mem: ipa_fw_region@9b080000 {
		no-map;
		reg = <0x0 0x9b080000 0x0 0x10000>;
	};

	ipa_gsi_mem: ipa_gsi_region@9b090000 {
		no-map;
		reg = <0x0 0x9b090000 0x0 0xa000>;
	};

	gpu_microcode_mem: gpu_microcode_region@9b09a000 {
		no-map;
		reg = <0x0 0x9b09a000 0x0 0x2000>;
	};

	spss_region_mem: spss_region_region@9b100000 {
		no-map;
		reg = <0x0 0x9b100000 0x0 0x180000>;
	};

	spu_secure_shared_memory_mem: spu_secure_shared_memory_region@9b280000 {
		no-map;
		reg = <0x0 0x9b280000 0x0 0x80000>;
	};

	camera_mem: camera_region@9b300000 {
		no-map;
		reg = <0x0 0x9b300000 0x0 0x800000>;
	};

	camera_2_mem: camera_2_region@9bb00000 {
		no-map;
		reg = <0x0 0x9bb00000 0x0 0x800000>;
	};

	video_mem: video_region@9c300000 {
		no-map;
		reg = <0x0 0x9c300000 0x0 0x800000>;
	};

	cvp_mem: cvp_region@9cb00000 {
		no-map;
		reg = <0x0 0x9cb00000 0x0 0x700000>;
	};

	cdsp_mem: cdsp_region@9d200000 {
		no-map;
		reg = <0x0 0x9d200000 0x0 0x2000000>;
	};

	q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9f200000 {
		no-map;
		reg = <0x0 0x9f200000 0x0 0x80000>;
	};

	q6_adsp_dtb_mem: q6_adsp_dtb_region@9f280000 {
		no-map;
		reg = <0x0 0x9f280000 0x0 0x80000>;
	};

	adspslpi_mem: adspslpi_region@9f300000 {
		no-map;
		reg = <0x0 0x9f300000 0x0 0x4080000>;
	};

	soccp_mem: soccp_region@a3380000 {
		no-map;
		reg = <0x0 0xa3380000 0x0 0x100000>;
	};

	/* uefi region can be reused by apps */

	/* Linux kernel image is loaded at 0xa8000000 */

	/* merged tz_reserved, xbl_sc, and qtee regions */
	tz_merged_mem: tz_merged_region@d8000000 {
		no-map;
		reg = <0x0 0xd8000000 0x0 0x600000>;
	};

	/*
	 * ta/tags mem is dynamically removed from the RAM
	 * partition tables before boot occurs. Size of region
	 * varies.
	 */

	trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0xf3800000 0x0 0x4400000>;
		reusable;
		alignment = <0x0 0x400000>;
	};

	oem_vm_mem: oem_vm_region@f7c00000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0xf7c00000 0x0 0x4c00000>;
		reusable;
		alignment = <0x0 0x400000>;
	};

	llcc_lpi_mem: llcc_lpi_region@ff800000 {
		no-map;
		reg = <0x0 0xff800000 0x0 0x800000>;
	};

	system_cma: linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0xC00000>;
		linux,cma-default;
	};
};

#include "sun-dma-heaps.dtsi"
#include "msm-arm-smmu-sun.dtsi"
#include "sun-pinctrl.dtsi"
#include "sun-regulators.dtsi"
#include "sun-qupv3.dtsi"
#include "sun-usb.dtsi"

&qupv3_se7_2uart {
	status = "ok";
};

#include "ipcc-test.dtsi"
/delete-node/ &ipcc_self_ping_adsp;
/delete-node/ &ipcc_self_ping_cdsp;
/delete-node/ &ipcc_self_ping_slpi;