// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa600000 0x100000>; reg-names = "core_base"; #address-cells = <2>; #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk"; resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_RISING>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,pm-qos-latency = <2>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ 0x120 /* GSI_DBL_ADDR_H */ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ usb-role-switch; interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&aggre2_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, <&aggre2_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; extcon = <&eud>; dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0 0xa600000 0x0 0xd800>; iommus = <&apps_smmu 0x540 0x0>; qcom,iommu-dma = "atomic"; memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; tx-fifo-resize; num-hc-interrupters = /bits/ 16 <3>; dr_mode = "otg"; maximum-speed = "super-speed"; usb-role-switch; }; port { usb_port0: endpoint { remote-endpoint = <&usb_port0_connector>; }; }; }; dwc3_mem_region: dwc3_mem_region { iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; }; /* USB port related High Speed PHY */ usb2_phy0: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e3000 0x11c>, <0x088e2000 0x4>; reg-names = "hsusb_phy_base", "eud_enable_reg"; vdd-supply = <&L5B>; vdda18-supply = <&L23B>; vdda33-supply = <&L25B>; qcom,vdd-voltage-level = <0 880000 920000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_EUSB3_0_CLKREF_EN>; clock-names = "ref_clk_src", "ref_clk"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; }; usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; /* USB port related QMP USB DP Combo PHY */ usb_qmp_dp_phy: ssphy@88e8000 { compatible = "qcom,usb-ssphy-qmp-dp-combo"; reg = <0x88e8000 0x3000>; reg-names = "qmp_phy_base"; vdd-supply = <&L7B>; qcom,vdd-voltage-level = <0 912000 912000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&L16B>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_0_CLKREF_EN>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "com_aux_clk", "ref_clk"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; pinctrl-names = "default"; pinctrl-0 = <&usb3phy_portselect_default>; qcom,qmp-phy-reg-offset = ; qcom,qmp-phy-init-seq = /* */ ; }; usb_audio_qmi_dev { compatible = "qcom,usb-audio-qmi-dev"; iommus = <&apps_smmu 0x100f 0x0>; qcom,iommu-dma = "disabled"; qcom,usb-audio-stream-id = <0xf>; qcom,usb-audio-intr-num = <2>; }; };