// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include "ravelin-pmic-overlay.dtsi"
#include "ravelin-pm7250b.dtsi"
#include "ravelin-thermal-overlay.dtsi"

&soc {
};

&qupv3_se1_spi {
	status = "ok";

	#address-cells = <1>;
	#size-cells = <0>;
	qcom,spi-touch-active = "focaltech,fts_ts";

	focaltech@0 {
		reg = <0x0>;
		spi-max-frequency = <6000000>;
		interrupt-parent = <&tlmm>;
		interrupts = <91 0x2008>;
		focaltech,reset-gpio = <&tlmm 90 0x00>;
		focaltech,irq-gpio = <&tlmm 91 0x2008>;
		focaltech,display-coords = <0 0 1080 2340>;
		focaltech,max-touch-number = <5>;
		focaltech,ic-type = <0x3658D488>;
		focaltech,touch-type = "primary";

		vdd-supply = <&L4E>;

		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
		pinctrl-0 = <&ts_spi_active>;
		pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
		pinctrl-2 = <&ts_spi_release>;
	};
};

&sdhc_1 {
	status = "ok";
	vdd-supply = <&L5E>;
	qcom,vdd-current-level = <0 570000>;

	vdd-io-supply = <&L19B>;
	qcom,vdd-io-always-on;
	qcom,vdd-io-lpm-sup;
	qcom,vdd-io-current-level = <0 325000>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc1_on>;
	pinctrl-1 = <&sdc1_off>;
};

&sdhc_2 {
	status = "ok";
	vdd-supply = <&L24B>;
	qcom,vdd-current-level = <0 800000>;

	/*
	 * min/max voltages are voted on L24B/L28B and L24B/L28B_PBS
	 * regulators will only be voted for enabling/disabling conditions
	 * to support FR84471 for chipsets where PMIC doesn't support
	 * PBS ram sequence to turn OFF regulators automatically on
	 * multicard tray removal and these new regulator resources are
	 * exposed by PMIC team as part of this FR.
	 */
	vdd-en-dis-supply = <&L24B_PBS>;

	vdd-io-supply = <&L28B>;
	qcom,vdd-io-voltage-level = <1800000 2960000>;
	qcom,vdd-io-current-level = <0 22000>;

	vdd-io-en-dis-supply = <&L28B_PBS>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_on>;
	pinctrl-1 = <&sdc2_off>;

	cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};

&ufsphy_mem {
	/*
	 * Here parrot phy is used for ravelin as it
	 * do not have its own list for module load and
	 * hence compatible is using parrot.
	 * We have plan to improve this by making phy binary
	 * target independent.
	 */
	compatible = "qcom,ufs-phy-qmp-v4-waipio";

	vdda-phy-supply = <&L5B>;
	vdda-pll-supply = <&L16B>;
	vdda-phy-max-microamp = <88530>;
	vdda-pll-max-microamp = <18310>;

	status = "ok";
};

&ufshc_mem {
	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;

	vcc-supply = <&L5E>;
	vcc-max-microamp = <1056000>;

	vccq-supply = <&L13B>;
	vccq-max-microamp = <750000>;

	vccq2-supply = <&L19B>;
	vccq2-max-microamp = <750000>;

	qcom,vddp-ref-clk-supply = <&L13B>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	/*
	 * ufs-dev-types and nvmem entries are for ufs device
	 * identification using nvmem interface. Use number of
	 * ufs devices supported for ufs-dev-types, and nvmem handle
	 * added by pmic for sdam register.
	 *
	 * Default value taken by driver is bit[0] = 0 for 3.x and
	 * bit[0] = 1 for 2.x driver code takes this as default case.
	 *
	 * But Bit value to identify ufs device is not consistent
	 * across the targets it could be bit[0] = 0/1 for UFS2.x/3x
	 * and vice versa. If the bit[0] value is not same as default
	 * value used in driver and if its reverted then use flag
	 * qcom,ufs-dev-revert to identify ufs device.
	 */
	ufs-dev-types = <2>;
	nvmem-cells = <&ufs_dev>, <&boot_config>;
	nvmem-cell-names = "ufs_dev", "boot_conf";

	boot_device_type = <0x0>;
	non-removable;

	status = "ok";
};

&battery_charger {
	qcom,thermal-mitigation-step = <500000>;
	qcom,wireless-charging-not-supported;
};