# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/qcom,msm_gpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies Inc GPI DMA controller

maintainers:
  - Mukesh Savaliya <quic_msavaliy@quicinc.com>

description: |
  QCOM GPI DMA controller provides DMA capabilities for
  peripheral buses such as I2C, UART, and SPI.

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    enum:
      - qcom,gpi-dma

  reg:
    maxItems: 1

  reg-names:
    maxItems: 1

  interrupts:
    description:
      Interrupt lines for each GPI instance
    minItems: 1
    maxItems: 12

  "#dma-cells":
    const: 3
    description: >
      DMA clients must use the format described in dma.txt, giving a phandle
      to the DMA controller plus the following 3 integer cells:
      - channel: if set to 0xffffffff, any available channel will be allocated
        for the client. Otherwise, the exact channel specified will be used.
      - seid: serial id of the client as defined in the SoC documentation.
      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h

  iommus:
    maxItems: 1

  qcom,max-num-gpii:
    maximum: 12

  qcom,gpii-mask:
    maxItems: 1

  qcom,static-gpii-mask:
    maxItems: 1

  qcom,ev-factor:
    maxItems: 1

  qcom,qcom,iommu-dma-addr-pool:
    maxItems: 1

  qcom,gpi-ee-offset:
    maxItems: 1

  dma-coherent:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - dma-cells
  - iommus
  - qcom,max-num-gpii
  - qcom,gpii-mask
  - qcom,ev-factor
  - qcom,qcom,iommu-dma-addr-pool
  - gpi-ee-offset

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/dma/qcom-gpi.h>
    gpi_dma1: qcom,gpi-dma@a00000  {
       compatible = "qcom,gpi-dma";
       #dma-cells = <5>;
       reg = <0xa00000  0x60000>;
       reg-names = "gpi-top";
       iommus = <&apps_smmu 0xb6 0x0>;
       qcom,max-num-gpii = <12>;
       interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
       qcom,static-gpii-mask = <0x3>;
       qcom,gpii-mask = <0xc>;
       qcom,ev-factor = <1>;
       qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
       qcom,gpi-ee-offset = <0x10000>;
       dma-coherent;
   };

...