// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>

&soc {
	usb0: ssusb@a600000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0xa600000 0x100000>;
		reg-names = "core_base";

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
			<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
					"utmi_clk", "sleep_clk";

		resets = <&gcc GCC_USB30_PRIM_BCR>;
		reset-names = "core_reset";

		interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pwr_event_irq";

		qcom,core-clk-rate = <200000000>;
		qcom,core-clk-rate-hs = <66666667>;
		qcom,core-clk-rate-disconnected = <133333333>;

		dwc3@a600000 {
			compatible = "snps,dwc3";
			reg = <0xa600000 0xd93c>;

			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			snps,disable-clk-gating;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x0>;
			snps,is-utmi-l1-suspend;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis_u2_susphy_quirk;
			snps,ssp-u3-u0-quirk;
			tx-fifo-resize;
			dr_mode = "otg";
			maximum-speed = "super-speed-plus";
			usb-role-switch;
		};
	};
};