// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,evacc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include <dt-bindings/clock/qcom,gpucc-tuna.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-tuna.h>
#include <dt-bindings/interconnect/qcom,tuna.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/spmi/spmi.h>

/ {
	model = "Qualcomm Technologies, Inc. Tuna";
	compatible = "qcom,tuna";
	qcom,msm-id = <655 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	memory {
		device_type = "memory";
		reg = <0 0 0 0>;
	};

	chosen: chosen {
		bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
	};

	reserved_memory: reserved-memory {};

	firmware: firmware {
		qcom_scm: qcom_scm {
			compatible = "qcom,scm";
			qcom,dload-mode = <&tcsr 0x19000>;
		};
	};

	aliases {
		serial0 = &qupv3_se7_2uart;
		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_2>;
			L2_2: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_3>;
			L2_3: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_4>;
			L2_4: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_5>;
			L2_5: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_6>;
			L2_6: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_7>;
			L2_7: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};

				core2 {
					cpu = <&CPU4>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU5>;
				};

				core1 {
					cpu = <&CPU6>;
				};
			};

			cluster3 {
				core0 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	idle-states {
		entry-method = "psci";

		GOLD_OFF_CL0: gold-cluster0-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <400>;
			exit-latency-us = <1100>;
			min-residency-us = <4011>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF_CL0: gold-cluster0-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <550>;
			exit-latency-us = <1050>;
			min-residency-us = <7951>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_OFF_CL1: gold-cluster1-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <400>;
			exit-latency-us = <1100>;
			min-residency-us = <4011>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF_CL1: gold-cluster1-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <550>;
			exit-latency-us = <1050>;
			min-residency-us = <7951>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_OFF_CL2: gold-cluster2-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <400>;
			exit-latency-us = <1100>;
			min-residency-us = <4011>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF_CL2: gold-cluster2-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <550>;
			exit-latency-us = <1050>;
			min-residency-us = <7951>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_PLUS_OFF: gold-plus-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <450>;
			exit-latency-us = <1200>;
			min-residency-us = <6230>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_PLUS_RAIL_OFF: gold-plus-cluster3-c4 { /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <500>;
			exit-latency-us = <1350>;
			min-residency-us = <7480>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		CLUSTER_PWR_DN: cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			idle-state-name = "l3-off";
			entry-latency-us = <750>;
			exit-latency-us = <2350>;
			min-residency-us = <9144>;
			arm,psci-suspend-param = <0x41000044>;
		};

		CX_RET: cx-ret { /* Cx Ret */
			compatible = "domain-idle-state";
			idle-state-name = "cx-ret";
			entry-latency-us = <1561>;
			exit-latency-us = <2801>;
			min-residency-us = <8550>;
			arm,psci-suspend-param = <0x41001344>;
		};

		APSS_OFF: cluster-e3 { /* E3 */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <2800>;
			exit-latency-us = <4400>;
			min-residency-us = <10150>;
			arm,psci-suspend-param = <0x4100b344>;
		};
	};

	soc: soc { };
};

#include "tuna-reserved-memory.dtsi"
#include "msm-arm-smmu-tuna.dtsi"
#include "tuna-dma-heaps.dtsi"

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* global autoconfigured region for contiguous allocations */
	system_cma: linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
		linux,cma-default;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD4: cpu-pd4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD5: cpu-pd5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD6: cpu-pd6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD7: cpu-pd7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: cluster-pd {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>;
		};
	};

	intc: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,	/* GICD */
		      <0x17180000 0x200000>;	/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
			      <0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};

	apps_rsc: rsc@17a00000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x17a00000 0x10000>,
		      <0x17a10000 0x10000>,
		      <0x17a20000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		qcom,drv-count = <3>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&CLUSTER_PD>;

		apps_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0xd00>;
			qcom,tcs-distance = <0x2a0>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    3>,
						  <SLEEP_TCS     2>,
						  <WAKE_TCS      2>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 1>;
			};

			apps_bcm_voter: bcm_voter {
				compatible = "qcom,bcm-voter";
			};
		};
	};

	cluster-device {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD>;
	};

	qcom,secure-buffer {
		compatible = "qcom,secure-buffer";
		qcom,vmid-cp-camera-preview-ro;
	};

	cam_rsc: rsc@adc8000 {
		label = "cam_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xadc8000 0x1000>,
		      <0xadc9000 0x1000>,
		      <0xadca000 0x1000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		qcom,drv-count = <3>;
		qcom,hw-channel;
		interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&camcc CAM_CC_DRV_AHB_CLK>;

		cam_rsc_drv0: drv@0 {
			qcom,drv-id = <0>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			channel@1 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};

		cam_rsc_drv1: drv@1 {
			qcom,drv-id = <1>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			channel@1 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};

		cam_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			channel@1 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <WAKE_TCS      1>,
						  <SLEEP_TCS     1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x1000>;
		reg-names = "drv-0";
		qcom,drv-count = <1>;
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;

		disp_rsc_drv0: drv@0 {
			qcom,drv-id = <0>;
			qcom,tcs-offset = <0x520>;
			qcom,tcs-distance = <0x150>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    0>,
						  <SLEEP_TCS     1>,
						  <WAKE_TCS      1>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,tuna-pdc", "qcom,pdc";
		reg = <0xb220000 0x10000>, <0x17c000f0 0x60>;
		qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
				  <10 230 1>, <11 724 1>, <12 716 1>,
				  <13 727 1>, <14 720 1>, <15 726 1>,
				  <16 721 1>, <17 262 1>, <18 70 1>,
				  <19 723 1>, <20 234 1>, <22 725 1>,
				  <23 231 1>, <24 504 14>, <40 520 6>,
				  <51 531 4>, <58 538 2>, <61 541 4>,
				  <67 547 27>, <94 609 31>, <125 63 1>,
				  <126 366 2>, <128 374 1>, <129 378 1>,
				  <130 428 1>, <131 434 2>, <133 437 1>,
				  <134 452 2>, <136 458 2>, <138 464 11>,
				  <149 671 1>, <150 688 1>, <151 714 2>,
				  <153 722 1>, <154 255 1>, <155 269 2>,
				  <157 276 1>, <158 287 1>, <159 306 4>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,tuna-tlmm";
		reg = <0x0f000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	ipcc_mproc: qcom,ipcc@406000 {
		compatible = "qcom,ipcc";
		reg = <0x406000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	aoss_qmp: power-controller@c300000 {
		compatible = "qcom,aoss-qmp";
		reg = <0xc300000 0x400>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		#power-domain-cells = <1>;
		#clock-cells = <0>;
	};

	qmp_aop: qcom,qmp-aop {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	qmp_tme: qcom,qmp-tme {
		compatible = "qcom,qmp-mbox";
		qcom,remote-pid = <14>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		mbox-names = "tme_qmp";
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;

		label = "tme";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};


	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_smem_mailbox_1_out: qcom,smp2p-smem-mailbox-1-out {
			qcom,entry-name = "smem-mailbox";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_smem_mailbox_1_in: qcom,smp2p-smem-mailbox-1-in {
			qcom,entry-name = "smem-mailbox";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-soccp {
		compatible = "qcom,smp2p";
		qcom,smem = <617>, <616>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <19>;

		soccp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		soccp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem_heap>;
		restrict-access;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_0_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_1_clk";
			#clock-cells = <0>;
		};

		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_tx_symbol_0_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	rpmhcc: clock-controller {
		compatible = "fixed-clock";
		clock-output-names = "rpmh_clocks";
		clock-frequency = <19200000>;
		#clock-cells = <1>;
	};

	cambistmclkcc: clock-controller@1760000 {
		compatible = "qcom,tuna-cambistmclkcc", "syscon";
		reg = <0x1760000 0x6000>;
		reg-name = "cc_base";
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&sleep_clk>,
			 <&gcc GCC_CAMERA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "sleep_clk",
			      "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};


	cam_crm: syscon@adcd600 {
		compatible = "syscon";
		reg = <0xadcd600 0x2000>;
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,tuna-camcc", "syscon";
		reg = <0xade0000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&sleep_clk>,
			 <&gcc GCC_CAMERA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "sleep_clk",
			      "iface";
		qcom,cam_crm-crmc = <&cam_crm>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,dummycc";
		clock-output-names = "dispcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	evacc: clock-controller@abf0000 {
		compatible = "qcom,tuna-evacc", "syscon";
		reg = <0xabf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&rpmhcc RPMH_CXO_CLK_A>,
			 <&sleep_clk>,
			 <&gcc GCC_EVA_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "bi_tcxo_ao",
			      "sleep_clk",
			      "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,tuna-gcc", "syscon";
		reg = <0x100000 0x1f4200>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&pcie_0_pipe_clk>,
			 <&sleep_clk>,
			 <&ufs_phy_rx_symbol_0_clk>,
			 <&ufs_phy_rx_symbol_1_clk>,
			 <&ufs_phy_tx_symbol_0_clk>,
			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
		clock-names = "bi_tcxo",
			      "pcie_0_pipe_clk",
			      "sleep_clk",
			      "ufs_phy_rx_symbol_0_clk",
			      "ufs_phy_rx_symbol_1_clk",
			      "ufs_phy_tx_symbol_0_clk",
			      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,tuna-gpucc", "syscon";
		reg = <0x3d90000 0x9800>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
			 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
		clock-names = "bi_tcxo",
			      "gpll0_out_main",
			      "gpll0_out_main_div";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	tcsrcc: clock-controller@1fbf000 {
		compatible = "qcom,tuna-tcsrcc", "syscon";
		reg = <0x1fbf000 0x14>;
		reg-name = "cc_base";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@aaf0000 {
		compatible = "qcom,tuna-videocc", "syscon";
		reg = <0xaaf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&rpmhcc RPMH_CXO_CLK_A>,
			 <&sleep_clk>,
			 <&gcc GCC_VIDEO_AHB_CLK>;
		clock-names = "bi_tcxo",
			      "bi_tcxo_ao",
			      "sleep_clk",
			      "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	tcsr: syscon@1fc0000 {
		compatible = "syscon";
		reg = <0x1fc0000 0x30000>;
	};

	clk_virt: interconnect@0 {
		compatible = "qcom,tuna-clk_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect@1 {
		compatible = "qcom,tuna-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	config_noc: interconnect@1600000 {
		compatible = "qcom,tuna-cnoc_cfg";
		reg = <0x1600000 0x9200>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	cnoc_main: interconnect@1500000 {
		compatible = "qcom,tuna-cnoc_main";
		reg = <0x1500000 0x16080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	system_noc: interconnect@1680000 {
		compatible = "qcom,tuna-system_noc";
		reg = <0x1680000 0x1d080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	pcie_noc: interconnect@16c0000 {
		compatible = "qcom,tuna-pcie_anoc";
		reg = <0x16c0000 0x11400>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	aggre1_noc: interconnect@16e0000 {
		compatible = "qcom,tuna-aggre1_noc";
		reg = <0x16e0000 0x16400>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	aggre2_noc: interconnect@1700000 {
		compatible = "qcom,tuna-aggre2_noc";
		reg = <0x1700000 0x1f400>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	mmss_noc: interconnect@1780000 {
		compatible = "qcom,tuna-mmss_noc";
		reg = <0x1780000 0x7d800>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	gem_noc: interconnect@24100000 {
		compatible = "qcom,tuna-gem_noc";
		reg = <0x24100000 0x14d080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	nsp_noc: interconnect@320c0000 {
		compatible = "qcom,tuna-nsp_noc";
		reg = <0x320c0000 0xe080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	lpass_ag_noc: interconnect@7e40000 {
		compatible = "qcom,tuna-lpass_ag_noc";
		reg = <0x7e40000 0xe080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	lpass_lpiaon_noc: interconnect@7400000 {
		compatible = "qcom,tuna-lpass_lpiaon_noc";
		reg = <0x7400000 0x19080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	lpass_lpicx_noc: interconnect@7420000 {
		compatible = "qcom,tuna-lpass_lpicx_noc";
		reg = <0x7420000 0x44080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x400000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
	};

	ufsphy_mem: ufsphy_mem@1d80000 {
		reg = <0x1d80000 0x2000>;
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;
		clock-names = "ref_clk_src",
			"ref_aux_clk", "qref_clk",
			"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
			"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
		clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
			<&tcsrcc TCSR_UFS_CLKREF_EN>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
			<&ufs_phy_rx_symbol_0_clk>,
			<&ufs_phy_rx_symbol_1_clk>,
			<&ufs_phy_tx_symbol_0_clk>;
		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>;
		reg-names = "ufs_mem";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;

		lanes-per-direction = <2>;
		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_LN_BB_CLK3>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<100000000 403000000>,
			<0 0>,
			<0 0>,
			<100000000 403000000>,
			<100000000 403000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		/* set the dependency that smmu being probed before ufs */
		depends-on-supply = <&apps_smmu>;

		iommus = <&apps_smmu 0x60 0x0>;
		qcom,iommu-dma = "bypass";
		dma-coherent;

		qcom,bypass-pbl-rst-wa;
		qcom,max-cpus = <8>;

		reset-gpios = <&tlmm 187 GPIO_ACTIVE_LOW>;
		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";

		status = "disabled";
	};

	spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
		compatible = "qcom,spmi-pmic-arb";
			reg = <0xc42d000 0x4000>,
			<0xc400000 0x3000>,
			<0xc500000 0x400000>,
			<0xc440000 0x80000>,
			<0xc4c0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <0>;
	};

	spmi1_bus: qcom,spmi@c432000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc432000 0x4000>,
			<0xc400000 0x3000>,
			<0xc500000 0x400000>,
			<0xc440000 0x80000>,
			<0xc4d0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <1>;
		depends-on-supply = <&spmi0_bus>;
		status = "disabled";
	};

	spmi0_debug_bus: qcom,spmi-debug@10b14000 {
		compatible = "qcom,spmi-pmic-arb-debug";
		reg = <0x10b14000 0x60>, <0x221c8784 0x4>;
		reg-names = "core", "fuse";
		clocks = <&aoss_qmp>;
		clock-names = "core_clk";
		qcom,fuse-enable-bit = <18>;
		#address-cells = <2>;
		#size-cells = <0>;
		depends-on-supply = <&spmi_bus>;

		pmk8550@0 {
			compatible = "qcom,spmi-pmic";
			reg = <0 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pmxr2230@1 {
			compatible = "qcom,spmi-pmic";
			reg = <1 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8550vs@3 {
			compatible = "qcom,spmi-pmic";
			reg = <3 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pmd802x@4 {
			compatible = "qcom,spmi-pmic";
			reg = <4 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8550ve@5 {
			compatible = "qcom,spmi-pmic";
			reg = <5 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8550vs@6 {
			compatible = "qcom,spmi-pmic";
			reg = <6 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pmg1110@8 {
			compatible = "qcom,spmi-pmic";
			reg = <8 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pmg1110@9 {
			compatible = "qcom,spmi-pmic";
			reg = <9 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pmr735d@a {
			compatible = "qcom,spmi-pmic";
			reg = <10 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8010@c {
			compatible = "qcom,spmi-pmic";
			reg = <12 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		pm8010@d {
			compatible = "qcom,spmi-pmic";
			reg = <13 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

	};

	thermal_zones: thermal-zones {
	};

	qcom,pmic_glink {
		compatible = "qcom,qti-pmic-glink";
		qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
		qcom,subsys-name = "lpass";
		qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
		depends-on-supply = <&ipcc_mproc>;

		battery_charger: qcom,battery_charger {
			compatible = "qcom,battery-charger";
		};

		ucsi: qcom,ucsi {
			compatible = "qcom,ucsi-glink";
		};

		altmode: qcom,altmode {
			compatible = "qcom,altmode-glink";
			#altmode-cells = <1>;
		};
	};

	qcom,pmic_glink_log {
		compatible = "qcom,qti-pmic-glink";
		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";

		qcom,battery_debug {
			compatible = "qcom,battery-debug";
		};

		qcom,charger_ulog_glink {
			compatible = "qcom,charger-ulog-glink";
		};

		pmic_glink_debug: qcom,pmic_glink_debug {
			compatible = "qcom,pmic-glink-debug";
			#address-cells = <1>;
			#size-cells = <0>;
			depends-on-supply = <&spmi1_bus>;

		};

		pmic_glink_adc: qcom,glink-adc {
			compatible = "qcom,glink-adc";
			#address-cells = <1>;
			#size-cells = <0>;
			#io-channel-cells = <1>;
			status = "disabled";
		};
	};
};

#include "tuna-gdsc.dtsi"

&cam_cc_ipe_0_gdsc {
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_ofe_gdsc {
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_tfe_0_gdsc {
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_tfe_1_gdsc {
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_tfe_2_gdsc {
	compatible = "qcom,gdsc";
	status = "ok";
};

&cam_cc_titan_top_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&disp_cc_mdss_core_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&disp_cc_mdss_core_int2_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&eva_cc_mvs0_gdsc {
	clocks = <&gcc GCC_EVA_AHB_CLK>;
	clock-names = "ahb_clk";
	status = "ok";
};

&eva_cc_mvs0c_gdsc {
	clocks = <&gcc GCC_EVA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&gcc_pcie_0_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_pcie_0_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_MX_LEVEL>;
	status = "ok";
};

&gcc_ufs_mem_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_MX_LEVEL>;
	status = "ok";
};

&gcc_ufs_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_usb30_prim_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_usb3_phy_gdsc {
	compatible = "qcom,gdsc";
	parent-supply = <&VDD_MX_LEVEL>;
	status = "ok";
};

&gpu_cc_cx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gx_clkctl_gx_gdsc {
	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
	status = "ok";
};

&video_cc_mvs0_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	status = "ok";
};

&video_cc_mvs0c_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
		compatible = "qcom,cmd-db";
		no-map;
		reg = <0x0 0x81c60000 0x0 0x20000>;
	};

	adsp_mem_heap: adsp_heap_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0xC00000>;
	};

	cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x4800000>;
	};
};

#include "tuna-pinctrl.dtsi"
#include "tuna-stub-regulators.dtsi"
#include "tuna-usb.dtsi"
#include "tuna-qupv3.dtsi"
#include "msm-rdbg.dtsi"
#include "tuna-pmic-overlay.dtsi"
#include "tuna-walt.dtsi"

&qupv3_se7_2uart {
	status = "ok";
};