// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/clock/qcom,dispcc-sun.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
#include "sun-sde-common.dtsi"

&soc {
	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
		compatible = "qcom,smmu_sde_unsec";
		iommus = <&apps_smmu 0x800 0x2>;
		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
		qcom,iommu-faults = "non-fatal";
		qcom,iommu-earlymap; /* for cont-splash */
		dma-coherent;
	};

	smmu_sde_sec: qcom,smmu_sde_sec_cb {
		compatible = "qcom,smmu_sde_sec";
		iommus = <&apps_smmu 0x801 0x0>;
		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
		qcom,iommu-faults = "non-fatal";
		qcom,iommu-vmid = <0xa>;
	};
};

&mdss_mdp {
	clocks =
		<&gcc GCC_DISP_HF_AXI_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
	clock-names = "gcc_bus",
			"iface_clk", "branch_clk", "core_clk", "vsync_clk",
			"lut_clk";
	clock-rate = <0 0 575000000 575000000 19200000 575000000>;
	clock-max-rate = <0 0 575000000 575000000 19200000 575000000>;

	vdd-supply = <&disp_cc_mdss_core_gdsc>;
	mmcx-supply = <&VDD_MMCX_LEVEL>;

	qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;

	qcom,sde-vm-exclude-reg-names = "ipcc_reg";

	/* data and reg bus scale settings */
	interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
			<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC
				&config_noc SLAVE_DISPLAY_CFG>;
	interconnect-names = "qcom,sde-data-bus0",
			"qcom,sde-ebi-bus", "qcom,sde-reg-bus";

	qcom,sde-has-idle-pc;

	qcom,sde-ib-bw-vote = <2500000 0 800000>;
	qcom,sde-dspp-ltm-version = <0x00010002>;
	/* offsets are based off dspp 0, 1, 2, and 3 */
	qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;

	qcom,platform-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,platform-supply-entry@0 {
			reg = <0>;
			qcom,supply-name = "mmcx";
			qcom,supply-min-voltage = <0>;
			qcom,supply-max-voltage = <0>;
			qcom,supply-enable-load = <0>;
			qcom,supply-disable-load = <0>;
		};

		qcom,platform-supply-entry@1 {
			reg = <1>;
			qcom,supply-name = "vdd";
			qcom,supply-min-voltage = <0>;
			qcom,supply-max-voltage = <0>;
			qcom,supply-enable-load = <0>;
			qcom,supply-disable-load = <0>;
		};
	};
};

&mdss_dsi0 {
	vdda-1p2-supply = <&L3G>;
	qcom,split-link-supported;
	clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
		<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_ESC0_CLK>,
		<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
			"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
};

&mdss_dsi1 {
	vdda-1p2-supply = <&L3G>;
	qcom,split-link-supported;
	clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
		<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_ESC1_CLK>,
		<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
			"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
};

&mdss_dsi_phy0 {
	vdda-0p9-supply = <&L3I>;
	qcom,panel-allow-phy-poweroff;
	qcom,dsi-pll-ssc-en;
	qcom,dsi-pll-ssc-mode = "down-spread";
	pll_codes_region = <&dsi_pll_codes_data>;

};

&mdss_dsi_phy1 {
	vdda-0p9-supply = <&L3I>;
	qcom,panel-allow-phy-poweroff;
	qcom,dsi-pll-ssc-en;
	qcom,dsi-pll-ssc-mode = "down-spread";
};