// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,dispcc-sun.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include "sun-sde-common.dtsi"

&soc {
	/* dummy display clock provider */
	clock_cpucc: qcom,cpucc {
		compatible = "qcom,dummycc";
		clock-output-names = "cpucc_clocks";
		#clock-cells = <1>;
	};

	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
		compatible = "qcom,smmu_sde_unsec";
		iommus = <&apps_smmu 0x804 0x2>;
		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
		qcom,iommu-faults = "non-fatal";
		dma-coherent;
	};
};

&mdss_mdp {
	reg = <0x0ae00000 0x93800>,
	      <0x0aeb0000 0x2008>,
	      <0x0af80000 0x7000>,
	      <0x0ae44000 0x02c>;

	reg-names = "mdp_phys",
		"vbif_phys",
		"regdma_phys",
		"sid_phys";

	qcom,sde-vm-exclude-reg-names = "sid_phys";

	qcom,tvm-include-reg = <0x0af20000 0x850>,
				<0xaf30000 0x60>,
				<0xaf31000 0x30>,
				<0xaf32000 0x30>,
				<0xaf33000 0x30>,
				<0xaf34000 0x30>,
				<0xaf35000 0x30>,
				<0xaf36000 0x30>;

	qcom,sde-hw-version =<0xC0000000>;

	clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
		<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
		<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
		<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
		<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
		<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
		<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
	clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
			"core_clk", "vsync_clk", "lut_clk";
	qcom,sde-trusted-vm-env;
};

&mdss_dsi0 {
	clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
		<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
		<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
		<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
			"pixel_clk", "pixel_clk_rcg", "esc_clk";
};

&mdss_dsi1 {
	clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
		<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
		<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
		<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
		<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
		<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
			"pixel_clk", "pixel_clk_rcg", "esc_clk";
};

&mdss_dsi_phy0 {
	qcom,dsi-pll-in-trusted-vm;
};

&mdss_dsi_phy1 {
	qcom,dsi-pll-in-trusted-vm;
};