// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,camcc-sm6150.h>
#include <dt-bindings/clock/qcom,dispcc-sm6150.h>
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/clock/qcom,videocc-sm6150.h>

/ {
	model = "Qualcomm Technologies, Inc. SM6150";
	compatible = "qcom,sm6150";
	qcom,msm-name = "SM6150";
	qcom,msm-id = <355 0x0>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		bootargs = "log_buf_len=2M earlycon=msm_geni_serial,0x880000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
	};

	memory { device_type = "memory"; reg = <0 0 0 0>; };


	reserved_memory: reserved-memory { };


	aliases: aliases { };

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-size = <0x100000>;
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_100>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			L2_100: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};


		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_200>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			L2_200: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_300>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			L2_300: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x400>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_400>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			L2_400: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x500>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_500>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			L2_500: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x600>;
			enable-method = "psci";
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <404>;
			cache-size = <0x10000>;
			next-level-cache = <&L2_600>;
			qcom,freq-domain = <&cpufreq_hw 1 2>;
			#cooling-cells = <2>;
			L2_600: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x700>;
			enable-method = "psci";
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <404>;
			cache-size = <0x10000>;
			next-level-cache = <&L2_700>;
			qcom,freq-domain = <&cpufreq_hw 1 2>;
			L2_700: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

			};

			cluster1 {
				core0 {
					cpu = <&CPU6>;
				};

				core1 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	soc: soc { };
};

	&reserved_memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_region: hyp_region@85700000 {
			no-map;
			reg = <0x0 0x85700000 0x0 0x600000>;
		};

		xbl_aop_mem: xbl_aop_mem@85e00000 {
			no-map;
			reg = <0x0 0x85e00000 0x0 0x120000>;
		};

		aop_cmd_db: memory@85f20000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85f20000 0x0 0x20000>;
			no-map;
		};

		sec_apps_mem: sec_apps_region@85fff000 {
			no-map;
			reg = <0x0 0x85fff000 0x0 0x1000>;
		};

		smem_region: smem@86000000 {
			no-map;
			reg = <0x0 0x86000000 0x0 0x200000>;
		};

		removed_region: removed_region@86200000 {
			no-map;
			reg = <0x0 0x86200000 0x0 0x2d00000>;
		};

		pil_camera_mem: camera_region@8ab00000 {
			no-map;
			reg = <0x0 0x8ab00000 0x0 0x500000>;
		};

		pil_modem_mem: modem_region@8b000000 {
			no-map;
			reg = <0x0 0x8b000000 0x0 0x8400000>;
		};

		pil_video_mem: pil_video_region@93400000 {
			no-map;
			reg = <0x0 0x93400000 0x0 0x500000>;
		};

		wlan_msa_mem: wlan_msa_region@93900000 {
			no-map;
			reg = <0x0 0x93900000 0x0 0x200000>;
		};

		pil_cdsp_mem: cdsp_regions@93b00000 {
			no-map;
			reg = <0x0 0x93b00000 0x0 0x1e00000>;
		};

		pil_adsp_mem: pil_adsp_region@95900000 {
			no-map;
			reg = <0x0 0x95900000 0x0 0x1e00000>;
		};

		pil_ipa_fw_mem: ips_fw_region@97700000 {
			no-map;
			reg = <0x0 0x97700000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: ipa_gsi_region@97710000 {
			no-map;
			reg = <0x0 0x97710000 0x0 0x5000>;
		};

		pil_gpu_mem: gpu_region@97715000 {
			no-map;
			reg = <0x0 0x97715000 0x0 0x2000>;
		};

		qseecom_mem: qseecom_region {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x9e400000 0x0 0x1400000>;
		};

		cdsp_sec_mem: cdsp_sec_regions@9f800000 {
			no-map;
			reg = <0x0 0x9f800000 0x0 0x1e00000>;
		};

		adsp_mem: adsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x800000>;
		};

		sdsp_mem: sdsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x400000>;
		};

		user_contig_mem: user_contig_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
		};

		sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		secure_display_memory: secure_display_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x8c00000>;
		};

		cont_splash_memory: splash_region {
			reg = <0x0 0x9c000000 0x0 0x0f00000>;
			label = "cont_splash_region";
		};

		dfps_data_memory: dfps_data_region@9cf00000 {
			reg = <0x0 0x9cf00000 0x0 0x0100000>;
			label = "dfps_data_region";
		};

		disp_rdump_memory: disp_rdump_region@9c000000 {
			reg = <0x0 0x9c000000 0x0 0x01000000>;
			label = "disp_rdump_region";
		};

		dump_mem: mem_dump_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			size = <0 0x2800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x2000000>;
			linux,cma-default;
		};
	};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	apps_rsc: rsc@18200000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x18200000 0x10000>,
		      <0x18210000 0x10000>,
		      <0x18220000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		qcom,drv-count = <3>;

		apps_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0xd00>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    2>,
						  <SLEEP_TCS     3>,
						  <WAKE_TCS      3>,
						  <CONTROL_TCS   1>,
						  <FAST_PATH_TCS 0>;
			};

			rpmhcc: qcom,rpmhclk {
				compatible = "qcom,sm6150-rpmh-clk";
				#clock-cells = <1>;
				status = "okay";
			};
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		qcom,drv-count = <1>;
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;

		disp_rsc_drv0: drv@0 {
			qcom,drv-id = <0>;
			qcom,tcs-offset = <0x1c00>;
			channel@0 {
				qcom,tcs-config = <SLEEP_TCS     1>,
						  <WAKE_TCS      1>,
						  <ACTIVE_TCS    2>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};
	};

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <1 9 4>;
		interrupt-parent = <&intc>;
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,sm6150-pdc", "qcom,pdc";
		reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 1 0xf08>,
			     <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 0 0xf08>;
		clock-frequency = <19200000>;
	};

	timer@17c20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@17c21000 {
			frame-number = <0>;
			interrupts = <0 8 0x4>,
				     <0 6 0x4>;
			reg = <0x17c21000 0x1000>,
			      <0x17c22000 0x1000>;
		};

		frame@17c23000 {
			frame-number = <1>;
			interrupts = <0 9 0x4>;
			reg = <0x17c23000 0x1000>;
			status = "disabled";
		};

		frame@17c25000 {
			frame-number = <2>;
			interrupts = <0 10 0x4>;
			reg = <0x17c25000 0x1000>;
			status = "disabled";
		};

		frame@17c27000 {
			frame-number = <3>;
			interrupts = <0 11 0x4>;
			reg = <0x17c27000 0x1000>;
			status = "disabled";
		};

		frame@17c29000 {
			frame-number = <4>;
			interrupts = <0 12 0x4>;
			reg = <0x17c29000 0x1000>;
			status = "disabled";
		};

		frame@17c2b000 {
			frame-number = <5>;
			interrupts = <0 13 0x4>;
			reg = <0x17c2b000 0x1000>;
			status = "disabled";
		};

		frame@17c2d000 {
			frame-number = <6>;
			interrupts = <0 14 0x4>;
			reg = <0x17c2d000 0x1000>;
			status = "disabled";
		};
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,sm6150-gcc", "syscon";
		reg = <0x100000 0x1f0000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&rpmhcc RPMH_CXO_CLK_A>,
			<&sleep_clk>;
		clock-names = "bi_tcxo",
			      "bi_tcxo_ao",
			      "sleep_clk";
		protected-clocks = <GCC_SDR_CORE_CLK>,
				   <GCC_SDR_WR0_MEM_CLK>,
				   <GCC_SDR_WR1_MEM_CLK>,
				   <GCC_SDR_WR2_MEM_CLK>,
				   <GCC_SDR_CSR_HCLK>,
				   <GCC_SDR_PRI_MI2S_CLK>,
				   <GCC_SDR_SEC_MI2S_CLK>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	camcc: clock-controller@ad00000 {
		compatible = "qcom,sm6150-camcc", "syscon";
		reg = <0xad00000 0x10000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "bi_tcxo";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,sm6150-dispcc", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
		clock-names = "bi_tcxo", "gpll0";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@5090000 {
		compatible = "qcom,sm6150-gpucc", "syscon";
		reg = <0x5090000 0x9000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "bi_tcxo", "gpll0";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@ab00000 {
		compatible = "qcom,sm6150-videocc", "syscon";
		reg = <0xab00000 0x10000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
		clock-names = "bi_tcxo", "sleep_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	apsscc: syscon@182a0000 {
		compatible = "syscon";
		reg = <0x182a0000 0x1c>;
	};

	mccc: syscon@90b0000 {
		compatible = "syscon";
		reg = <0x90b0000 0x54>;
	};

	debugcc: debug-clock-controller@0 {
		compatible = "qcom,sm6150-debugcc";
		qcom,apsscc = <&apsscc>;
		qcom,camcc = <&camcc>;
		qcom,dispcc = <&dispcc>;
		qcom,gcc = <&gcc>;
		qcom,gpucc = <&gpucc>;
		qcom,mccc = <&mccc>;
		qcom,videocc = <&videocc>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo_clk_src";
		#clock-cells = <1>;
	};

	cpufreq_hw: cpufreq@18323000 {
		compatible = "qcom,cpufreq-hw";
		reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
		reg-names = "freq-domain0", "freq-domain1";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "xo", "alternate";
		#freq-domain-cells = <2>;
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	qcom_tzlog: tz-log@146aa720 {
		compatible = "qcom,tz-log";
		reg = <0x146aa720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
	};

	kryo-erp {
		compatible = "arm,arm64-kryo-cpu-erp";
		interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "l1-l2-faultirq",
					"l1-l2-errirq",
					"l3-scu-errirq",
					"l3-scu-faultirq";
	};

	tlmm: pinctrl@03000000 {
		compatible = "qcom,sm6150-pinctrl";
		reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>;
		reg-names = "pinctrl", "spi_cfg";
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		qcom,gpios-reserved = <0 1 2 3 6 7 8 9>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;
	};

	apss_shared: mailbox@17c00000 {
		compatible = "qcom,sm8150-apss-shared";
		reg = <0x17c00000 0x1000>;
		#mbox-cells = <1>;
	};

	aoss_qmp: power-controller@c300000 {
		compatible = "qcom,aoss-qmp";
		reg = <0xc300000 0x400>;
		interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apss_shared 0>;

		#clock-cells = <0>;
		#power-domain-cells = <1>;
	};

	qmp_aop: qmp-aop {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	apcs: syscon@17c0000c {
		compatible = "syscon";
		reg = <0x17c0000c 0x4>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock@1f40000 {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem@8600000 {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		hwlocks = <&tcsr_mutex 3>;
	};

	glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};
	};

	smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
			qcom,entry-name = "wlan";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom_smp2p_adsp: smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 26>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 6>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
				qcom,entry-name = "master-kernel";
				#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
				qcom,entry-name = "slave-kernel";
				interrupt-controller;
				#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
				qcom,entry-name = "rdbg";
				#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};

#include "sm6150-regulator.dtsi"
#include "sm6150-gdsc.dtsi"
#include "sm6150-pinctrl.dtsi"
#include "msm-rdbg.dtsi"

&tlmm {
	status = "okay";
};

&emac_gdsc {
	status = "ok";
};

&pcie_0_gdsc {
	status = "ok";
};

&ufs_phy_gdsc {
	status = "ok";
};

&usb30_prim_gdsc {
	status = "ok";
};

&usb20_sec_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
	status = "ok";
};

&titan_top_gdsc {
	parent-supply = <&VDD_MX_LEVEL>;
	status = "ok";
};

&bps_gdsc {
	qcom,support-hw-trigger;
	status = "ok";
};

&ife_0_gdsc {
	status = "ok";
};

&ife_1_gdsc {
	status = "ok";
};

&ipe_0_gdsc {
	qcom,support-hw-trigger;
	status = "ok";
};

&mdss_core_gdsc {
	status = "ok";
};

&gpu_cx_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_gx_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&vcodec0_gdsc {
	qcom,support-hw-trigger;
	status = "ok";
};

&venus_gdsc {
	status = "ok";
};