// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

&soc {
	msm_mmrm_test: qcom,mmrm-test {
		compatible = "qcom,msm-mmrm-test", "qcom,tuna-mmrm-test";
		status = "disable";

		/* Clock info */
		clock-names =
			"cam_cc_camnoc_rt_axi_clk_src",
			"cam_cc_csid_clk_src",
			"cam_cc_icp_0_clk_src",
			"cam_cc_icp_1_clk_src",
			"cam_cc_ife_lite_clk_src",
			"cam_cc_ipe_nps_clk_src",
			"cam_cc_jpeg_clk_src",
			"cam_cc_ofe_clk_src",
			"cam_cc_tfe_0_clk_src",
			"cam_cc_tfe_1_clk_src",
			"cam_cc_tfe_2_clk_src",
			"cam_cc_fast_ahb_clk_src",
			"cam_cc_slow_ahb_clk_src",
			"cam_cc_cci_0_clk_src",
			"cam_cc_cci_1_clk_src",
			"cam_cc_cci_2_clk_src",
			"cam_cc_cre_clk_src",
			"cam_cc_csi0phytimer_clk_src",
			"cam_cc_csi1phytimer_clk_src",
			"cam_cc_csi2phytimer_clk_src",
			"cam_cc_csi3phytimer_clk_src",
			"cam_cc_csi4phytimer_clk_src",
			"cam_cc_csi5phytimer_clk_src",
			"cam_cc_cphy_rx_clk_src",
			"cam_cc_ife_lite_csid_clk_src",
			"eva_cc_mvs0_clk_src",
			"disp_cc_mdss_mdp_clk_src",
			"video_cc_mvs0_clk_src";

		clocks =
			<&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>,
			<&camcc CAM_CC_CSID_CLK_SRC>,
			<&camcc CAM_CC_ICP_0_CLK_SRC>,
			<&camcc CAM_CC_ICP_1_CLK_SRC>,
			<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
			<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
			<&camcc CAM_CC_JPEG_CLK_SRC>,
			<&camcc CAM_CC_OFE_CLK_SRC>,
			<&camcc CAM_CC_TFE_0_CLK_SRC>,
			<&camcc CAM_CC_TFE_1_CLK_SRC>,
			<&camcc CAM_CC_TFE_2_CLK_SRC>,
			<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
			<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
			<&camcc CAM_CC_CCI_0_CLK_SRC>,
			<&camcc CAM_CC_CCI_1_CLK_SRC>,
			<&camcc CAM_CC_CCI_2_CLK_SRC>,
			<&camcc CAM_CC_CRE_CLK_SRC>,
			<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
			<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
			<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
			<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
			<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
			<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
			<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
			<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
			<&evacc EVA_CC_MVS0_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
			<&videocc VIDEO_CC_MVS0_CLK_SRC>;

		/*
		 * clock_data : domain, clock-ID,
		 * rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO,
		 * num_hw_blocks, hw_drv_instances, num_pwr_states
		 */
		clock_data =
			<0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC	300000000	400000000	400000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_CSID_CLK_SRC		400000000	480000000	480000000	480000000	480000000	1	0	0>,
			<0x1 CAM_CC_ICP_0_CLK_SRC		400000000	480000000	600000000	600000000	600000000	1	0	0>,
			<0x1 CAM_CC_ICP_1_CLK_SRC		400000000	480000000	600000000	600000000	600000000	1	0	0>,
			<0x1 CAM_CC_IFE_LITE_CLK_SRC		400000000	480000000	480000000	480000000	480000000	1	0	0>,
			<0x1 CAM_CC_IPE_NPS_CLK_SRC		450000000	575000000	675000000	825000000	825000000	1	0	0>,
			<0x1 CAM_CC_JPEG_CLK_SRC		200000000	400000000	480000000	600000000	600000000	1	0	0>,
			<0x1 CAM_CC_OFE_CLK_SRC			436000000	570000000	675000000	757000000	757000000	1	0	0>,
			<0x1 CAM_CC_TFE_0_CLK_SRC		400000000	525000000	644000000	750000000	750000000	1	0	0>,
			<0x1 CAM_CC_TFE_1_CLK_SRC		400000000	525000000	644000000	750000000	750000000	1	0	0>,
			<0x1 CAM_CC_TFE_2_CLK_SRC		400000000	525000000	644000000	750000000	750000000	1	0	0>,
			<0x1 CAM_CC_FAST_AHB_CLK_SRC		300000000	300000000	300000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_SLOW_AHB_CLK_SRC		80000000	80000000	80000000	80000000	80000000	1	0	0>,
			<0x1 CAM_CC_CCI_0_CLK_SRC		37500000	37500000	37500000	37500000	37500000	1	0	0>,
			<0x1 CAM_CC_CCI_1_CLK_SRC		37500000	37500000	37500000	37500000	37500000	1	0	0>,
			<0x1 CAM_CC_CCI_2_CLK_SRC		37500000	37500000 	37500000	37500000	37500000	1	0	0>,
			<0x1 CAM_CC_CRE_CLK_SRC			200000000	400000000	480000000	600000000	600000000	1	0	0>,
			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC	400000000	400000000	400000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC	400000000	400000000	400000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC	400000000	400000000	400000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC	400000000	400000000	400000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC	400000000	400000000	400000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC	400000000	400000000	400000000	400000000	400000000	1	0	0>,
			<0x1 CAM_CC_CPHY_RX_CLK_SRC		400000000	480000000	480000000	480000000	480000000	10	0	0>,
			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC	400000000	480000000	480000000	480000000	480000000	2	0	0>,
			<0x1 EVA_CC_MVS0_CLK_SRC		350000000	450000000	500000000	550000000	550000000	1	0	0>,
			<0x1 DISP_CC_MDSS_MDP_CLK_SRC		207000000	342000000	417000000	535000000	600000000	1	0	0>,
			<0x1 VIDEO_CC_MVS0_CLK_SRC		338000000	3360000000	444000000	444000000	533000000	1	0	0>;
	};
};