// SPDX-License-Identifier: BSD-3-Clause

/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interconnect/qcom,x1e80100.h>

&tlmm {
	cnss_pins {
		cnss_wlan_en_active: cnss_wlan_en_active {
			mux {
				pins = "gpio117";
				function = "gpio";
			};

			config {
				pins = "gpio117";
				drive-strength = <16>;
				output-high;
				bias-pull-up;
			};
		};

		cnss_wlan_en_sleep: cnss_wlan_en_sleep {
			mux {
				pins = "gpio117";
				function = "gpio";
			};

			config {
				pins = "gpio117";
				drive-strength = <2>;
				output-low;
				bias-pull-down;
			};
		};
	};
};

&reserved_memory {
	cnss_wlan_mem: cnss_wlan_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x4000000>;
	};
};

&soc {
	wlan_kiwi: qcom,cnss-kiwi@b0000000 {
		compatible = "qcom,cnss-kiwi";
		reg = <0xb0000000 0x10000>;
		reg-names = "smmu_iova_ipa";
		qcom,wlan-cbc-enabled;
		supported-ids = <0x1107>;
		wlan-en-gpio = <&tlmm 117 0>;
		qcom,bt-en-gpio = <&tlmm 116 0>;
		pinctrl-names = "wlan_en_active", "wlan_en_sleep";
		pinctrl-0 = <&cnss_wlan_en_active>;
		pinctrl-1 = <&cnss_wlan_en_sleep>;
		qcom,wlan;
		qcom,wlan-rc-num = <4>;
		qcom,wlan-ramdump-dynamic = <0x780000>;
		cnss-enable-self-recovery;
		use-pm-domain;
		qcom,same-dt-multi-dev;
		qcom,qmp = <&aoss_qmp>;
		vdd-wlan-m2-supply = <&vreg_wlan_3p3>;
		qcom,vdd-wlan-m2-config = <3300000 3300000 0 0 0>;
		vdd-wlan-io-supply = <&L15B>;
		qcom,vdd-wlan-io-config = <1800000 1800000 0 0 0>;
		/* interconnect is not set */
	};
};

&pcie4_rp {
	cnss_pci0: cnss_pci0 {
		reg = <0 0 0 0 0>;
		qcom,iommu-group = <&cnss_pci_iommu_group0>;
		memory-region =
			<&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;

		#address-cells = <1>;
		#size-cells = <1>;

		cnss_pci0_iommu_region_partition:
		cnss_pci0_iommu_region_partition {
			iommu-addresses =
				<&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
				<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
		};

		cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
			qcom,iommu-msi-size = <0x1000>;
			qcom,iommu-geometry = <0xa0000000 0x10010000>;
			/* bypass due to SMMU V3 is NOT well supported yet */
			qcom,iommu-dma = "bypass";
			qcom,iommu-pagetable = "coherent";
			qcom,iommu-faults =
				"stall-disable", "HUPCF", "non-fatal";
		};
	};
};