// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-kera.h>

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	qcom,msm-id = <659 0x10000>, <686 0x10000>;
	interrupt-parent = <&vgic>;

	chosen {
		bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force rcupdate.rcu_expedited=1 rcu_nocbs=0-1";
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		CPU0: cpu@0 {
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			cpu-idle-states = <&CPU_PWR_DWN
					   &CLUSTER_PWR_DWN>;
		};

		CPU1: cpu@100 {
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			cpu-idle-states = <&CPU_PWR_DWN
					   &CLUSTER_PWR_DWN>;

		};
	};

	idle-states {
		CPU_PWR_DWN: c4 {  /* Using Medium C4 latencies */
			compatible = "arm,idle-state";
			status = "disabled";
		};

		CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
			compatible = "arm,idle-state";
			status = "disabled";
		};
	};

	qcom,vm-config {
		compatible = "qcom,vm-1.0";
		vm-type = "aarch64-guest";
		boot-config = "fdt,unified";
		os-type = "linux";
		kernel-entry-segment = "kernel";
		kernel-entry-offset = <0x0 0x0>;
		vendor = "QTI";
		image-name = "qcom,trustedvm";
		qcom,pasid = <0x0 0x1c>;
		qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;";
		qcom,secdomain-ids = <45>;
		qcom,primary-vm-index = <0>;
		vm-uri = "vmuid/trusted-ui";
		vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
		qcom,sensitive;

		vm-attrs = "context-dump", "crash-restart";

		iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
				0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;

		/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
		 * QUP1_SE4: GPII5 : IRQ_316
		 * QUP2_SE7: GPII5 : IRQ_625
		 */
		gic-irq-ranges = <316 316
				  625 625 /* PVM->SVM IRQ transfer */
				  279 279>;

		memory {
			#address-cells = <0x2>;
			#size-cells = <0x0>;
			/*
			 * IPA address linux image is loaded at. Must be within
			 * first 1GB due to memory hotplug requirement.
			 */
			base-address = <0x0 0x88800000 >;
		};

		segments {
			config_cpio = <2>;
		};

		vcpus {
			config = "/cpus";
			affinity = "proxy";
			affinity-map = <0x0 0x0>;
			sched-priority = <0>;       /* relative to PVM */
			sched-timeslice = <2000>;   /* in ms */
		};

		interrupts {
			config = &vgic;
		};

		vdevices {
			generate = "/hypervisor";

			minidump {
				vdevice-type = "minidump";
				push-compatible = "qcom,minidump_rm";
				minidump_allowed;
			};

			rm-rpc {
				vdevice-type = "rm-rpc";
				generate = "/hypervisor/qcom,resource-mgr";
				console-dev;
				message-size = <0x000000f0>;
				queue-depth = <0x00000008>;
				qcom,label = <0x1>;
			};

			virtio-mmio@0 {
				vdevice-type = "virtio-mmio";
				generate = "/virtio-mmio";
				peer-default;
				vqs-num = <0x1>;
				push-compatible = "virtio,mmio";
				dma-coherent;
				dma_base = <0x0 0x0>;
				memory {
					qcom,label = <0x11>;			//for persist.img
					#address-cells = <0x2>;
					base = <0x0 0xDA6F8000>;
				};
			};

			virtio-mmio@1 {
				vdevice-type = "virtio-mmio";
				generate = "/virtio-mmio";
				peer-default;
				vqs-num = <0x2>;
				push-compatible = "virtio,mmio";
				dma-coherent;
				dma_base = <0x0 0x4000>;
				memory {
					qcom,label = <0x10>;			//for system.img
					#address-cells = <0x2>;
					base = <0x0 0xDA6FC000>;
				};
			};

			virtio-mmio@2 {
				vdevice-type = "virtio-mmio";
				patch = "/soc/virtio-mmio";
				peer-default;
				vqs-num = <0x3>;
				push-compatible = "virtio,mmio";
				dma-coherent;
				dma_base = <0x0 0x8000>;
				memory {
					qcom,label = <0x15>;			//for virtio-vsock
					#address-cells = <0x2>;
					base = <0x0 0xDA700000>;
				};
			};

			swiotlb-shm {
				vdevice-type = "shm";
				generate = "/swiotlb";
				push-compatible = "swiotlb";
				peer-default;
				dma_base = <0x0 0x14000>;
				memory {
					qcom,label = <0x12>;
					#address-cells = <0x2>;
					base = <0x0 0xDA70c000>;
				};
			};

			vrtc {
				vdevice-type = "vrtc-pl031";
				peer-default;
				allocate-base;
			};

			mem-buf-message-queue-pair {
				vdevice-type = "message-queue-pair";
				generate = "/hypervisor/membuf-msgq-pair";
				message-size = <0x000000f0>;
				queue-depth = <0x00000008>;
				peer-default;
				qcom,label = <0x0000001>;
			};
		};
	};

	firmware: firmware {
		qcom_scm: qcom_scm {
			compatible = "qcom,scm";
		};
	};

	soc: soc { };
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	gcc: clock-controller@100000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	virtio-mmio {
		wakeup-source;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	vgic: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,	/* GICD */
		      <0x17180000 0x200000>;	/* GICR * 8 */
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		always-on;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	qcom_smcinvoke {
		compatible = "qcom,smcinvoke";
	};

	qcom_mem_object {
		compatible = "qcom,mem-object";
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
		qcom,custom-bridge-size = <64>;
		qcom,support-hypervisor;
	};

	qcom,mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "consumer";
		qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
		qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */
		qcom,vmid = <45>;
	};

	mem_buf_msgq: qcom,mem-buf-msgq {
		compatible = "qcom,mem-buf-msgq";
		qcom,msgq-names = "trusted_vm";
	};

	virtio_mem_device {
		compatible = "qcom,virtio-mem";
		depends-on-supply = <&mem_buf_msgq>;
		/* Must be memory_block_size_bytes() aligned */
		qcom,max-size = <0x0 0x18000000>;
		qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
		qcom,block-size = <0x400000>;
		qcom,initial-movable-zone-size = <0x2000000>;

	};

	/*
	 * QUP1 : SE0 - Secondary touch
	 * QUP2 : SE0 - Primary touch
	 */
	qup_iommu_group: qup_common_iommu_group {
		iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
				<&qupv3_1 0x00000000 0x00020000>,
				<&gpi_dma2 0x00000000 0x00020000>,
				<&qupv3_2 0x00000000 0x00020000>;
	};

	/* GPI Instance */
	gpi_dma1: qcom,gpi-dma@a00000 {
		compatible = "qcom,gpi-dma";
		reg = <0xa00000 0x60000>;
		#dma-cells = <5>;
		reg-names = "gpi-top";
		iommus = <&apps_smmu 0xb8 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		dma-coherent;
		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
		qcom,max-num-gpii = <12>;
		qcom,static-gpii-mask = <0x20>;
		qcom,gpii-mask = <0x0>;
		qcom,ev-factor = <1>;
		qcom,gpi-ee-offset = <0x10000>;
		qcom,le-vm;
		status = "ok";
	};

	/* QUPv3_1 wrapper instance */
	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0xac0000 0x2000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clock-names = "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		iommus = <&apps_smmu 0xb8 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		dma-coherent;
		ranges;
		status = "ok";

		/* Secondary Tounch */
		qupv3_se0_i2c: i2c@a80000 {
			compatible = "qcom,i2c-geni";
			reg = <0xa80000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&gpi_dma1 0 0 3 64 0xc>,
				<&gpi_dma1 1 0 3 64 0xc>;
			dma-names = "tx", "rx";
			qcom,le-vm;
			status = "disabled";
		};

		/* Secondary Touch */
		qupv3_se0_spi: spi@a80000 {
			compatible = "qcom,spi-geni";
			reg = <0xa80000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "se_phys";
			dmas = <&gpi_dma1 0 0 1 64 0xc>,
				<&gpi_dma1 1 0 1 64 0xc>;
			dma-names = "tx", "rx";
			spi-max-frequency = <50000000>;
			qcom,le-vm;
			status = "disabled";
		};
	};

	/* GPI Instance */
	gpi_dma2: qcom,gpi-dma@800000 {
		compatible = "qcom,gpi-dma";
		reg = <0x800000 0x60000>;
		#dma-cells = <5>;
		reg-names = "gpi-top";
		iommus = <&apps_smmu 0x438 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		dma-coherent;
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
		qcom,max-num-gpii = <12>;
		qcom,static-gpii-mask = <0x20>;
		qcom,gpii-mask = <0x0>;
		qcom,ev-factor = <1>;
		qcom,gpi-ee-offset = <0x10000>;
		qcom,le-vm;
		status = "ok";
	};

	/* QUPv3_2 wrapper instance */
	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0x8c0000 0x2000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clock-names = "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		iommus = <&apps_smmu 0x438 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		dma-coherent;
		ranges;
		status = "ok";

		/* Touchscreen I2C Instance */
		qupv3_se8_i2c: i2c@880000 {
			compatible = "qcom,i2c-geni";
			reg = <0x880000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&gpi_dma2 0 0 3 64 0xc>,
				<&gpi_dma2 1 0 3 64 0xc>;
			dma-names = "tx", "rx";
			qcom,le-vm;
			status = "disabled";
		};

		/* Touchscreen SPI Instance */
		qupv3_se8_spi: spi@880000 {
			compatible = "qcom,spi-geni";
			reg = <0x880000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "se_phys";
			dmas = <&gpi_dma2 0 0 1 64 0xc>,
				<&gpi_dma2 1 0 1 64 0xc>;
			dma-names = "tx", "rx";
			spi-max-frequency = <50000000>;
			qcom,le-vm;
			status = "disabled";
		};
	};
};

#include "msm-arm-smmu-kera-vm.dtsi"
#include "kera-vm-dma-heaps.dtsi"