// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include &tlmm { cnss_pins { cnss_wlan_en_active: cnss_wlan_en_active { mux { pins = "gpio16"; function = "gpio"; }; config { pins = "gpio16"; drive-strength = <16>; output-high; bias-pull-up; }; }; cnss_wlan_en_sleep: cnss_wlan_en_sleep { mux { pins = "gpio16"; function = "gpio"; }; config { pins = "gpio16"; drive-strength = <2>; output-low; bias-pull-down; }; }; cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl { mux { pins = "gpio18"; function = "wcn_sw_ctrl"; }; }; cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx { mux { pins = "gpio19"; function = "wcn_sw"; }; }; cnss_host_sol_default: cnss_host_sol_default { mux { pins = "gpio204"; function = "gpio"; }; config { pins = "gpio204"; drive-strength = <4>; bias-pull-down; }; }; }; }; &reserved_memory { cnss_wlan_mem: cnss_wlan_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; size = <0x0 0x2000000>; }; }; &soc { wlan_peach: qcom,cnss-peach@b0000000 { compatible = "qcom,cnss-peach"; reg = <0x0 0xb0000000 0x0 0x10000>; reg-names = "smmu_iova_ipa"; qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>; supported-ids = <0x110E>; wlan-en-gpio = <&tlmm 16 0>; qcom,bt-en-gpio = <&pmh0104_gpios 5 0>; qcom,sw-ctrl-gpio = <&tlmm 18 0>; wlan-host-sol-gpio = <&tlmm 204 0>; wlan-dev-sol-gpio = <&tlmm 205 0>; /* List of GPIOs to be setup for interrupt wakeup capable */ mpm_wake_set_gpios = <18 19>; pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl", "sw_ctrl_wl_cx", "sol_default"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; pinctrl-2 = <&cnss_wlan_sw_ctrl>; pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>; pinctrl-4 = <&cnss_host_sol_default>; qcom,wlan; qcom,wlan-rc-num = <0>; qcom,wlan-ramdump-dynamic = <0x780000>; cnss-enable-self-recovery; qcom,wlan-cbc-enabled; use-pm-domain; qcom,same-dt-multi-dev; /* For AOP communication, use direct QMP instead of mailbox */ qcom,qmp = <&aoss_qmp>; msix-match-addr = <0x3000>; vdd-wlan-aon-supply = <&L2G>; qcom,vdd-wlan-aon-config = <1800000 1800000 30000 0 1>; vdd-wlan-io12-supply = <&L3G>; qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>; vdd-wlan-cx-supply = <&S1J>; qcom,vdd-wlan-cx-config = <892000 1000000 0 0 1>; vdd-wlan-dig-supply = <&S2J>; qcom,vdd-wlan-dig-config = <892000 1000000 0 0 1>; vdd-wlan-rfa1-supply = <&S8F>; qcom,vdd-wlan-rfa1-config = <1876000 2000000 0 0 1>; vdd-wlan-rfa2-supply = <&S7F>; qcom,vdd-wlan-rfa2-config = <1328000 1340000 0 0 1>; qcom,vreg_pdc_map = "s1j", "bb", "s2j", "rf", "s7f", "rf", "s8f", "rf"; qcom,pmu_vreg_map = "VDD_PMU_AON_I", "s2j", "VDD09_PMU_RFA_I", "s2j", "VDD19_PMU_RFA_I", "s8f", "VDD13_PMU_RFA_I", "s7f", "VDD095_MX_PMU", "s2j", "VDD095_PMU_CX", "s1j", "VDD095_PMU_BTCX", "s2j", "VDD095_PMU_BTMX", "s2j", "VDD13_PMU_PCIE_I", "s7f", "VDD13_PMU_PCIE12_I", "s7f"; /* cpu mask used for wlan tx rx interrupt affinity * */ wlan-txrx-intr-cpumask = <0x3 0x30>; }; }; &pcie0_rp { cnss_pci0: cnss_pci0 { reg = <0 0 0 0 0>; qcom,iommu-group = <&cnss_audio_iommu_group0>; memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>; cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition { /* address-cells =3 size-cells=2 from canoe-pcie.dtsi */ iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x18000000>, <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>; }; }; };