# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/msm-eva.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. MSM CVP

description: |
  Root level node - cvp

properties:
  # A dictionary of DT properties for this binding schema
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,msm-cvp
              - qcom,sun-cvp
              - qcom,pineapple-cvp
              - qcom,kalama-cvp
              - qcom,waipio-cvp
              - qcom,lahaina-cvp
              - qcom,kona-cvp

  reg:
    description:
      offset and length of the CSR register set for the device.
  interrupts:
    description:
      should contain the cvp interrupt.
  qcom,reg-presets:
    description:
      list of offset-value pairs for registers to be written.
      The offsets are from the base offset specified in 'reg'. This is mainly
      used for QoS, VBIF, etc. presets for video.
  qcom,qdss-presets:
    description:
      list of physical address and memory allocation size pairs.
      when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware
      messages will be written to QDSS memory.
  ‘*-supply’:
    description:
      A phandle pointing to the appropriate regulator. Number of
      regulators vary across targets.
  clock-names:
    description:
      an array of clocks that the driver is supposed to be
      manipulating. The clocks names here correspond to the clock names
      used in clk_get(<name>).
  qcom,clock-configs:
    description:
      an array of bitmaps of clocks' configurations. The index of the
      bitmap corresponds to the clock at the same index in qcom,clock-names.
      The bitmaps describes the actions that the device needs to take
      regarding the clock (i.e. scale it based on load).
      The bitmap is defined as scalable = 0x1
      (if the driver should vary the clock's frequency based on load)
  qcom,allowed-clock-rates:
    description:
      an array of supported clock rates by the chipset.
  qcom,use-non-secure-pil:
    description:
      A bool indicating which type of pil to use to load the fw.
  qcom,fw-bias:
    description:
      The address at which cvp fw is loaded (manually).

required:
  - compatible

examples:
  - |
    msm_cvp: qcom,cvp@ab00000 {
        compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
        status = "ok";
        reg = <0xab00000 0x100000>;
        interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;

        /* FIXME: LLCC Info */
        /* cache-slice-names = "vidsc0", "vidsc1"; */
        /* cache-slices = <&llcc 2>, <&llcc 3>; */

        /* Supply */
        cvp-supply = <&mvs1_gdsc>;

        /* Clocks */
        clock-names =  "gcc_video_axi0",
            "gcc_video_axi1", "cvp_clk";
        clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
            <&clock_gcc GCC_VIDEO_AXI1_CLK>,
            <&clock_videocc VIDEO_CC_MVS1_CLK>;
        qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
            "cvp_clk";

        qcom,clock-configs = <0x0 0x0 0x1>;
        qcom,allowed-clock-rates = <403000000 520000000
            549000000 666000000 800000000>;

        /* Buses */
        bus_cnoc {
            compatible = "qcom,msm-cvp,bus";
            label = "cnoc";
            qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
            qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
            qcom,bus-governor = "performance";
            qcom,bus-range-kbps = <1000 1000>;
        };

        /* MMUs */
        non_secure_cb {
            compatible = "qcom,msm-cvp,context-bank";
            label = "cvp_hlos";
            iommus = <&apps_smmu 0x2120 0x400>;
            qcom,iommu-dma = "disabled";
            buffer-types = <0xfff>;
            virtual-addr-pool = <0x4b000000 0xe0000000>;
        };

        /* Memory Heaps */
        qcom,msm-cvp,mem_cdsp {
            compatible = "qcom,msm-cvp,mem-cdsp";
            memory-region = <&cdsp_mem>;
        };
    };