// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/clock/qcom,gpucc-kera.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-tuna.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>

/ {
	model = "Qualcomm Technologies, Inc. Kera";
	compatible = "qcom,kera";
	qcom,msm-id = <659 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	memory {
		device_type = "memory";
		reg = <0 0 0 0>;
	};

	chosen: chosen {
		bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
	};

	reserved_memory: reserved-memory {};

	firmware: firmware {};

	aliases {};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_2>;
			L2_2: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_3>;
			L2_3: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_4>;
			L2_4: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_5>;
			L2_5: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_6>;
			L2_6: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "spin-table"; /* TODO: Update to psci */
			cpu-release-addr = <0x0 0xE3940000>;
			next-level-cache = <&L2_7>;
			L2_7: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU3>;
				};

				core1 {
					cpu = <&CPU4>;
				};

				core2 {
					cpu = <&CPU5>;
				};

				core3 {
					cpu = <&CPU6>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	soc: soc { };
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,	/* GICD */
		      <0x17180000 0x200000>;	/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
			      <0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,kera-tlmm";
		reg = <0xf000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	ipcc_mproc: qcom,ipcc@406000 {
		compatible = "qcom,ipcc";
		reg = <0x406000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_1_pipe_clk: pcie_1_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_0_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_1_clk";
			#clock-cells = <0>;
		};

		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_tx_symbol_0_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	rpmhcc: clock-controller {
		compatible = "fixed-clock";
		clock-output-names = "rpmh_clocks";
		clock-frequency = <19200000>;
		#clock-cells = <1>;
	};

	cambistmclkcc: clock-controller@1760000 {
		compatible = "qcom,dummycc";
		clock-output-names = "cambistmclkcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,dummycc";
		clock-output-names = "camcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,dummycc";
		clock-output-names = "dispcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,dummycc";
		clock-output-names = "gpucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	tcsrcc: clock-controller@1f40000 {
		compatible = "qcom,dummycc";
		clock-output-names = "tcsrcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@aaf0000 {
		compatible = "qcom,dummycc";
		clock-output-names = "videocc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};
};

#include "tuna-gdsc.dtsi"

&cam_cc_ipe_0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_ofe_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_tfe_0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_tfe_1_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_tfe_2_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&cam_cc_titan_top_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&disp_cc_mdss_core_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&disp_cc_mdss_core_int2_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_0_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_1_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_pcie_1_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_ufs_mem_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_ufs_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_usb30_prim_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gcc_usb3_phy_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&gpu_cc_cx_gdsc_hw_ctrl {
	reg = <0x3d99124 0x4>;
};

&gpu_cc_cx_gdsc {
	compatible = "regulator-fixed";
	reg = <0x3d99110 0x4>;
	status = "ok";
};

&gpu_cc_gx_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&video_cc_mvs0_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

&video_cc_mvs0c_gdsc {
	compatible = "regulator-fixed";
	status = "ok";
};

#include "kera-pinctrl.dtsi"