// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/soc/qcom,ipcc.h>
#include "sdx75.dtsi"
/delete-node/ &apps_smmu;
#include "msm-arm-smmu-sdxkova.dtsi"
/{
	qcom_tzlog: tz-log@14680720 {
		compatible = "qcom,tz-log";
		reg = <0x0 0x14680720 0x0 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
	};

	/delete-node/ reserved-memory;

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		system_cma: linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x2000000>;
			linux,cma-default;
		};
	};

	soc: soc {
		/delete-node/ rsc@17a00000;

		apps_rsc: rsc@17a00000 {
			label = "apps_rsc";
			compatible = "qcom,rpmh-rsc";
			reg = <0x0 0x17a00000 0x0 0x10000>,
			      <0x0 0x17a10000 0x0 0x10000>,
			      <0x0 0x17a20000 0x0 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,drv-count = <3>;

			apps_rsc_drv2: drv@2 {
				qcom,drv-id = <2>;
				qcom,tcs-offset = <0xd00>;
				channel@0 {
					qcom,tcs-offset = <0xd00>;
					qcom,tcs-config = <ACTIVE_TCS    3>,
							  <SLEEP_TCS     2>,
							  <WAKE_TCS      2>,
							  <FAST_PATH_TCS 0>,
							  <CONTROL_TCS   0>;
				};

			};
		};

		apps_bcm_voter: bcm-voter {
			compatible = "qcom,bcm-voter";
		};

		rpmhcc: clock-controller {
			compatible = "qcom,sdx75-rpmh-clk";
			clocks = <&xo_board>;
			clock-names = "xo";
			#clock-cells = <1>;
		};

		rpmhpd: power-controller {
			compatible = "qcom,sdx75-rpmhpd";
			#power-domain-cells = <1>;
			operating-points-v2 = <&rpmhpd_opp_table>;

			rpmhpd_opp_table: opp-table {
				compatible = "operating-points-v2";

				rpmhpd_opp_ret: opp-16 {
					opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
				};

				rpmhpd_opp_min_svs: opp-48 {
					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
				};

				rpmhpd_opp_low_svs: opp-64 {
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				rpmhpd_opp_svs: opp-128 {
					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				rpmhpd_opp_svs_l1: opp-192 {
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				};

				rpmhpd_opp_nom: opp-256 {
					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
				};

				rpmhpd_opp_nom_l1: opp-320 {
					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				};

				rpmhpd_opp_nom_l2: opp-336 {
					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
				};

				rpmhpd_opp_turbo: opp-384 {
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
				};

				rpmhpd_opp_turbo_l1: opp-416 {
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
				};
			};
		};
	};

	aliases: aliases {
		serial0 = &uart1;
	};
};

&clk_virt {
	#interconnect-cells = <1>;
	qcom,bcm-voter-names = "hlos";
};

&mc_virt {
	#interconnect-cells = <1>;
	qcom,bcm-voter-names = "hlos";
};

&system_noc {
	#interconnect-cells = <1>;
	qcom,bcm-voter-names = "hlos";
	clocks = <&gcc GCC_SYS_NOC_MVMSS_CLK>;
};

&pcie_anoc {
	#interconnect-cells = <1>;
	qcom,bcm-voter-names = "hlos";
};

&dc_noc {
	#interconnect-cells = <1>;
	qcom,bcm-voter-names = "hlos";
};

&gem_noc {
	#interconnect-cells = <1>;
	qcom,bcm-voter-names = "hlos";
};

&tlmm {
	gpio-reserved-ranges = <110 6>;
};

&qupv3_id_0 {
	status = "ok";
};

&uart1 {
	status = "ok";
};

#include "sdxkova-regulators.dtsi"

&chosen {
	bootargs = "cpufreq.default_governor=performance";
};

&soc {

	clocks {
		emac0_sgmiiphy_mac_rclk: emac0_sgmiiphy_mac_rclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac0_sgmiiphy_mac_rclk";
			#clock-cells = <0>;
		};

		emac0_sgmiiphy_mac_tclk: emac0_sgmiiphy_mac_tclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac0_sgmiiphy_mac_tclk";
			#clock-cells = <0>;
		};

		emac0_sgmiiphy_rclk: emac0_sgmiiphy_rclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac0_sgmiiphy_rclk";
			#clock-cells = <0>;
		};

		emac0_sgmiiphy_tclk: emac0_sgmiiphy_tclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac0_sgmiiphy_tclk";
			#clock-cells = <0>;
		};

		emac1_sgmiiphy_mac_rclk: emac1_sgmiiphy_mac_rclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac1_sgmiiphy_mac_rclk";
			#clock-cells = <0>;
		};

		emac1_sgmiiphy_mac_tclk: emac1_sgmiiphy_mac_tclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac1_sgmiiphy_mac_tclk";
			#clock-cells = <0>;
		};

		emac1_sgmiiphy_rclk: emac1_sgmiiphy_rclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac1_sgmiiphy_rclk";
			#clock-cells = <0>;
		};

		emac1_sgmiiphy_tclk: emac1_sgmiiphy_tclk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "emac1_sgmiiphy_tclk";
			#clock-cells = <0>;
		};

		pcie20_phy_aux_clk: pcie20_phy_aux_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie20_phy_aux_clk";
			#clock-cells = <0>;
		};

		pcie_1_pipe_clk: pcie_1_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_2_pipe_clk: pcie_2_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_2_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_pipe_clk: pcie_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_pipe_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	/* GCC GDSCs */
	gcc_emac0_gdsc: qcom,gdsc@f1004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xf1004 0x0 0x4>;
		regulator-name = "gcc_emac0_gdsc";
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_emac1_gdsc: qcom,gdsc@f2004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xf2004 0x0 0x4>;
		regulator-name = "gcc_emac1_gdsc";
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_pcie_1_gdsc: qcom,gdsc@e7004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xe7004 0x0 0x4>;
		regulator-name = "gcc_pcie_1_gdsc";
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_pcie_1_phy_gdsc: qcom,gdsc@d6004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xd6004 0x0 0x4>;
		regulator-name = "gcc_pcie_1_phy_gdsc";
		parent-supply = <&VDD_MXA_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_pcie_2_gdsc: qcom,gdsc@e8004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xe8004 0x0 0x4>;
		regulator-name = "gcc_pcie_2_gdsc";
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_pcie_2_phy_gdsc: qcom,gdsc@ee004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xee004 0x0 0x4>;
		regulator-name = "gcc_pcie_2_phy_gdsc";
		parent-supply = <&VDD_MXA_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_pcie_gdsc: qcom,gdsc@d3004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xd3004 0x0 0x4>;
		regulator-name = "gcc_pcie_gdsc";
		parent-supply = <&VDD_MXA_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_pcie_phy_gdsc: qcom,gdsc@d4004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xd4004 0x0 0x4>;
		regulator-name = "gcc_pcie_phy_gdsc";
		parent-supply = <&VDD_MXA_LEVEL>;
		qcom,retain-regs;
		qcom,support-hw-trigger;
	};

	gcc_usb30_gdsc: qcom,gdsc@a7004 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xa7004 0x0 0x4>;
		regulator-name = "gcc_usb30_gdsc";
		parent-supply = <&VDD_MXA_LEVEL>;
		qcom,retain-regs;
	};

	gcc_usb3_phy_gdsc: qcom,gdsc@a8008 {
		compatible = "qcom,gdsc";
		reg = <0x0 0xa8008 0x0 0x4>;
		regulator-name = "gcc_usb3_phy_gdsc";
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,retain-regs;
	};

	apsscc: syscon@17aa0000 {
		compatible = "syscon";
		reg = <0x0 0x17aa0000 0x0 0x1c>;
	};

	mccc: syscon@190ba000 {
		compatible = "syscon";
		reg = <0x0 0x190ba000 0x0 0x54>;
	};

	debugcc: clock-controller@0 {
		compatible = "qcom,sdx75-debugcc";
		qcom,apsscc = <&apsscc>;
		qcom,gcc = <&gcc>;
		qcom,mccc = <&mccc>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc 0>;
		clock-names = "xo_clk_src",
			"gcc";
		#clock-cells = <1>;
	};

	qcom,cpufreq-hw-debug {
		compatible = "qcom,cpufreq-hw-epss-debug";
		qcom,freq-hw-domain = <&cpufreq_hw 0>;
	};

	ipcc_mproc: qcom,ipcc@408000 {
		compatible = "qcom,ipcc";
		reg = <0x0 0x408000 0x0 0x1000>;
		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	llcc_device: cache-controller@19200000 {
		compatible = "qcom,sdxpinn-llcc";
		reg = <0x0 0x19200000 0x0 0x200000>;
		reg-names = "llcc0_base";
		interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
		cap-based-alloc-and-pwr-collapse;
	};
};

&gcc {
	compatible = "qcom,sdx75-gcc", "syscon";
	reg = <0x0 0x0080000 0x0 0x1f7400>;
	vdd_cx-supply = <&VDD_CX_LEVEL>;
	vdd_mx-supply = <&VDD_MXA_LEVEL>;
	clocks = <&rpmhcc RPMH_CXO_CLK>,
		 <&emac0_sgmiiphy_mac_rclk>,
		 <&emac0_sgmiiphy_mac_tclk>,
		 <&emac0_sgmiiphy_rclk>,
		 <&emac0_sgmiiphy_tclk>,
		 <&emac1_sgmiiphy_mac_rclk>,
		 <&emac1_sgmiiphy_mac_tclk>,
		 <&emac1_sgmiiphy_rclk>,
		 <&emac1_sgmiiphy_tclk>,
		 <&pcie20_phy_aux_clk>,
		 <&pcie_1_pipe_clk>,
		 <&pcie_2_pipe_clk>,
		 <&pcie_pipe_clk>,
		 <&sleep_clk>,
		 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
	clock-names = "bi_tcxo",
		      "emac0_sgmiiphy_mac_rclk",
		      "emac0_sgmiiphy_mac_tclk",
		      "emac0_sgmiiphy_rclk",
		      "emac0_sgmiiphy_tclk",
		      "emac1_sgmiiphy_mac_rclk",
		      "emac1_sgmiiphy_mac_tclk",
		      "emac1_sgmiiphy_rclk",
		      "emac1_sgmiiphy_tclk",
		      "pcie20_phy_aux_clk",
		      "pcie_1_pipe_clk",
		      "pcie_2_pipe_clk",
		      "pcie_pipe_clk",
		      "sleep_clk",
		      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
	protected-clocks = <GCC_TLMM_125_CLK>,
			<GCC_TLMM_125_CLK_SRC>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};

#include "sdxkova-usb.dtsi"
#include "ipcc-test-sdxkova.dtsi"