// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include #include &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-niobe"; /* VDDA_UFS_CORE */ vdda-phy-supply = <&L6B>; vdda-phy-max-microamp = <211860>; /* VDDA_UFS_0_1P2 */ vdda-pll-supply = <&L4B>; vdda-pll-max-microamp = <18330>; /* Phy GDSC for VDD_MX, always on */ vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; /* Qref power supply, Refer Qref diagram */ vdda-qref-supply = <&L2B>; vdda-qref-max-microamp = <1890>; clock-names = "ref_clk_src", "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&tcsrcc TCSR_UFS_CLKREF_EN>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>; status = "ok"; }; &ufshc_mem { vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vcc-supply = <&L12B>; vcc-max-microamp = <800000>; vccq2-supply = <&L1D>; vccq2-max-microamp = <750000>; /* VDD_PX10 is voted for the ufs_reset_n */ qcom,vddp-ref-clk-supply = <&L3G>; qcom,vddp-ref-clk-max-microamp = <100>; qcom,vccq2-parent-supply = <&S1B>; qcom,vccq2-parent-max-microamp = <210000>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&clk8_a4>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <100000000 403000000>, <0 0>, <0 0>, <100000000 403000000>, <100000000 403000000>, <0 0>, <0 0>, <0 0>, <0 0>; status = "ok"; };