#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {
	msm_fastrpc: qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,rpc-latency-us = <235>;
		qcom,fastrpc-gids = <2908>;
		qcom,qos-cores = <0 1 2 3>;

		fastrpc_compute_cb1: qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0xC0B 0x0>;
			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
			qrtr-gen-pool = <&fastrpc_compute_cb1>;
			frpc-gen-addr-pool = <0x8000 0x9000>;
			pd-type = <4>;	/* SECURE_STATICPD */
		};
	};

	qrtr-genpool {
		compatible = "qcom,qrtr-genpool";
		gen-pool = <&fastrpc_compute_cb1>;
		interrupt-parent = <&ipcc_mproc_ns1>;
		interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
				<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
				<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
	};
};