Yuanfang Zhang
fcac16f9c7
ARM: dts: msm: move scandump_gpu to dynamic memory dump
...
Move scandump_gpu dump entry to dynamic memory dump.
Change-Id: I5682b7f335482a84bee0539765f7124a82544161
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-06-17 13:26:53 +08:00
Yuanfang Zhang
10e5f31ee5
ARM: dts: msm: move spr/cpuss_reg to dynamic dump
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Move spr/cpuss_reg dump entry to dynamic dump.
Change-Id: I9cb30827a86d6d03ed6eb14ecf6cf9b3b059ea7b
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-06-03 07:49:16 -07:00
Yuanfang Zhang
18c5b67de5
ARM: dts: msm: Use reserved memory instead of CMA
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Use reserved memory instead of CMA for memdump node. The dump entries
are divided into two groups, one is static_dump, entries in this group
are enabled by default during startup. dynamic_dump is the other group,
entries in this group can be enabled/disabled after startup and disabled
on perf build.
Change-Id: I4f40cc29e2920cd0b2dd6b6b7285a770f1b39b3e
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-06-03 13:43:44 +08:00
Bruce Levy
fc71b2f0a1
Revert "ARM: dts: msm: move cpu related dump entry to dynamic mem dump"
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This reverts commit 5deaa15089quic_blevy@quicinc.com >
2024-04-30 19:27:15 -07:00
Yuanfang Zhang
5deaa15089
ARM: dts: msm: move cpu related dump entry to dynamic mem dump
...
Move cpu related dump entries to dynamic mem dump, the reserved memory
of these entries can be reclaimed if this dump entry is not enabled.
Change-Id: I222b7e00e3d074b58c0fb6ba42f16fe2f33d842e
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-04-16 01:59:58 -07:00
Yuanfang Zhang
2f7905c2c7
ARM: dts: msm: disable scandump_ubwcp dumps on Sun
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Disable scandump_ubwcp memory dumps on Sun.
Change-Id: I87e1a34338060a41d90acf0ccd4aaf52f24a5087
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-03-12 01:39:56 -07:00
Yuanfang Zhang
a4fed79f2a
ARM: dts: msm: add dcc sram offset on Sun
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Set dcc sram offset to 0x800 on Sun.
Change-Id: I3881a71fc5aab9cb42451ac815864e86930e3afa
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-02-21 14:45:22 +08:00
Yuanfang Zhang
eac98d95d7
ARM: dts: msm: add memory dump entry for TZ Core context on sun
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Add memory dump entry of TZ Core context for sun.
Change-Id: I6a5c9190dc91a2e2843dd60b979c1b06c9ce603b
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-01-16 18:57:27 -08:00
Yuanfang Zhang
1b7411497c
ARM: dts: msm: add cluster cache dump entry on sun
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Add cluster cache memory dump entry for sun.
Change-Id: I5dfcaa4e34e961a8eceef1ccf4b7a1d300f2bb47
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2024-01-05 00:10:36 -08:00
Jerome Lee
df64193218
ARM: dts: msm: Add register lists to DCC for Sun
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Add register lists to DCC for Sun.
Change-Id: Iffec4f0022a11be7fb5e0701e37975d71a1e9428
Signed-off-by: Jerome Lee <quic_jaewookl@quicinc.com >
2023-11-30 21:49:05 -08:00
Yuanfang Zhang
f2e93ba80b
ARM: dts: msm: correct dcc sram size on sun
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correct dcc sram size to 0x8000 on sun.
Change-Id: I1c4458390101d9d9026977ca71e95fad74667f05
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2023-11-19 21:39:16 -08:00
Yuanfang Zhang
d39b93f626
ARM: dts: msm: add cpu related dump for sun
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Add cpu related dump entry for sun.
Change-Id: Idf8723bc0e04fb87822a37d271361d2da0baa690
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2023-11-14 02:45:01 -08:00
Yuanfang Zhang
103a530725
ARM: dts: msm: correct size for reserved dump_mem on sun
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Correct the reserved dump_mem size on sun.
Change-Id: Ic7c4843f5789d2d75cdc19d2762e9e2651544996
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2023-11-09 21:02:59 -08:00
Yuanfang Zhang
01986ee6f6
ARM: dts: msm: add dump table for sun
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Add memory dump table for sun.
Change-Id: I1ed6ad897b7bf1be878821475c5270a406efb3d7
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2023-11-07 02:40:59 -08:00
Yuanfang Zhang
2964e2edd2
ARM: dts: msm: add coresight component DT file for sun
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Add coresight component devicetree file for sun.
Change-Id: I28b8b6a2142fc89ed457553f039eca785064007b
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com >
2023-09-19 23:21:39 -07:00
