Add ddr-regions device tree node in Tuna and Kera to optimize
boot-up time as firmware will look for this node during boot
and if it finds it early, it will save some time in bootup.
Change-Id: If3d6f3be7331870b5ecec9834de1dbebfbb6c22f
Signed-off-by: Shivendra Pratap <quic_spratap@quicinc.com>
Previous commit c0ad941ff4 ("ARM: dts: msm: Add bootargs for tuna
and kera") reverted couple of other change due to merge conflict
and merge itself. Add the affected change again to fix the issue.
Change-Id: I469075244ad34f13ea7004baae9d9423ebc4584d
Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Add support for cpufreq_hw and cpufreq_hw_debug nodes on tuna platform.
While at it, set the default governor to performance on tuna platform.
Change-Id: I2a0b89d51a16c479da35ca60286b2df18c3fba55
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Add initial set of DCVS device nodes for Tuna. This
includes the QCOM DCVS devices, PMU device memlat device
nodes and mapping tables, and bwmon device nodes.
Change-Id: I3abb2b912f22198f375635f0214bdbd0e71d5d5a
Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
Remove #address-cells and #size-cells properties from the cpucp
node as they are identical to those in the parent node,
allowing them to be inherited.
Change-Id: Ief29334722acf4e525d4d510a54840c26d3e594a
Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
Add dsi_pll_codes and disp_rdump_region nodes in the
beginning of devicetree to optimize the bootloader
search for these nodes during bootup which reduces
bootup time.
Change-Id: I7b7fe798a9d0daf306d76bc34132574ba6e0e88e
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add pmd802x support for tuna mtp platforms.
While at it add pm7550ba thermal zones and other pm7550ba support.
Change-Id: Ia34757eecea578b454c83c24610d8bdb31e2836b
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Fix the SDC2 GPIO pin function names to match the tuna-pinctrl driver.
The function name like "SDC2_CMD" was incorrectly written as "sdc2_cmd"
and etc. This alignment ensures proper functioning.
Change-Id: I4fd35d3c7d4fbdf0ee1bc32ad81efc3088529265
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Add RPMH regulator devices for SMPS, LDO regulators,
found on the PMIC chips used on tuna boards, to ensure that
consumers are able to modify the physical state of these regulators.
Change-Id: Ie30bbc8ab04d75246a5ff902841981c907dc9fca
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Even though we use proxy scheduling, during VM bootup hypervisor tries
to boot the VMs as per the affinity-map. This may cause panic in case a
CPU within affinity-map is unavailable.
Affining vCPUs to CPU0 makes sure VM proceeds with
powered-ON sequence, assuming CPU0 is always available.
Change-Id: Ia6799445891e1b003b5055178adb50778bade863
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Add support for rpmh clock controller nodes on TUNA platform.
While at it, keep rpmhcc node as dummy for TUNA rumi platform.
Change-Id: I97b2a42df7886295efd8b4a176257fe45a571bae
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
Add pmih010x support for tuna.
While at it add sys-therm-11 for tuna.
Change-Id: Idc08213fdadb300d0eb793f422ecf9b210785db9
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Add cma regions for tuivm and oemvm, inline with v1.
Change-Id: I117ad4bd3af4fb1c9c3c5bf046fdf903d3ddb99d
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
The high speed phy is required for USB to support HS
usecases. Add eusb node on tuna which includes the
necessary resources for the eusb phy to work.
Additional: Added interrupts for tuna.
Change-Id: Ifa3484bd52f876804b455e46a67a3b7b28fc663d
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
In this change adding memory region for iommu node
for tuna.
Change-Id: I50bc3d510bfab93bc5bfc22c2e3c44b9c450c8f1
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
Add cma regions for tuivm and oemvm, inline with v2.
Change-Id: I72263dfc41eb0ecafb38bdac42e685483ba6d66c
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
