Commit Graph

13 Commits

Author SHA1 Message Date
Yuhui Zhao
8ab4f13077 ARM: dts: msm: correct the port mask of mbhc port
Correct the port mask of mbhc port.
Since the WCD_SWR_TX DATA0 voltage was incorrect
with default setting, but was correct when
the ADC_LP was running in the swrm bus 9.6mhz,
So copy the SWR_UC0(9.6mhz) to SWR_UC1(4.8mhz).

Change-Id: I3638349a6ebec06b8f4a828498e1285579361e45
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
2025-03-26 13:47:44 +08:00
Ravulapati Vishnu Vardhan Rao
78c03916fe ARM: dts: msm: update clk div factor entry for TX and VA macros
Update clk div factor entries for TX and VA macros to reflect
proper HW configuration.

Change-Id: Ic5456d7e30245a484b6a4888835c7e6f838eb92b
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2025-02-25 19:50:30 +05:30
Ravulapati Vishnu Vardhan Rao
904d4e888a ARM: dts: msm: Enable external display on Kera
Ebnable external display on all the Kera variants.

Change-Id: I1448b3144f6cecf4282d9f87fd9c00c59f67328f
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2025-01-06 19:41:03 -08:00
QCTECMDR Service
109db1db3a Merge "ARM: dts: msm: update primary i2s pin" 2024-12-30 08:01:24 -08:00
Kisan Yadav
1e8205fd73 ARM: dts: msm: Update kera overlay dtsi
-Add cdc_dmic_gpio's in kera overlay dtsi.
-As part dmic event, msm pinctrl state is checked, The node should
 already be parsed and cached during machine probe.

Change-Id: I2cdd410274df99d463a2ba01d00f315754fd831f
Signed-off-by: Kisan Yadav <quic_kisany@quicinc.com>
2024-12-30 03:55:48 -08:00
Ravulapati Vishnu Vardhan Rao
f0adcad997 ARM: dts: msm: Enable BT on Kera variants
Enable BT for slimbus validation.

Change-Id: I0d96cb75016712459878231f05072d22eee3d6bf
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2024-12-29 23:38:25 -08:00
Ravulapati Vishnu Vardhan Rao
1f9c246241 ARM: dts: msm: update primary i2s pin
- As in IPCAT there is a conflicting info about
  PIN configuration, Corrected as per discussion
  with IPS.
- Removal of I2S0_DATA1 pin, as GPIO_63 is not
  used internally for I2S purpose and it is being
  used by other subsystem.


Change-Id: Ie1788565e7a4f47a167108de2e3ada3ac099da7e
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2024-12-27 10:44:46 -08:00
Yuhui Zhao
8a5e454114 ARM: dts: msm: correct wsa channel of kera qrd
Correct wsa channel of kera qrd. it should
be left channel.

Change-Id: I8b784e77b2db45963d0e27a47a51fc145febb52b
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
2024-12-04 22:46:54 -08:00
Ravulapati Vishnu Vardhan Rao
6338ab11b7 ARM: dts: msm: Change GIC and gpio
Update GIC as per IPCAT the GIC number is incorrect.
722 will not get interrupts of HSJ and audio will be mute.
Changing this to 721 as in tuna same issue was observing.

correction of wrong gpio pin.

Change-Id: Idb87af4d1438186ed29fc3227d447f1b6d189676
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2024-11-29 22:08:02 -08:00
Ravulapati Vishnu Vardhan Rao
8c9dc8e8bc ARM: dts: msm: Replace swr nodes
Replace swr node with default as swr core does not detect.

Change-Id: Ibe40453c70867c9687bd01ca9345dae8080bafac
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2024-11-29 22:07:25 -08:00
Ravulapati Vishnu Vardhan Rao
fded148f66 ARM: dts: msm: Revert BOB and usbss
This change reverts the commented section of BOB and
wcd_usbss as they are depended on kernel change.

Change-Id: I9fad7ce9732d7ec776ee3f14142129e406398c0f
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2024-11-27 18:43:56 -08:00
Ravulapati Vishnu Vardhan Rao
2a172de4f4 ARM: dts: msm: comment BOB and usbss
Need to revert once kernel changes are in place.

Change-Id: I96caf7ca9b78421b9c25b6ddc5ef6fd2a71b9d9a
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2024-11-13 18:12:02 -08:00
Ravulapati Vishnu Vardhan Rao
efe96d7aa4 ARM: dts: msm: Add support for platforms for Kera
Add audio device tree support for ATP, CDP, MTP, QRD, RCM
platforms for Kera SoC.

Change-Id: I902e8704d07cafe118047b152d83979f57cbf334
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
2024-11-13 19:41:49 +05:30