Add bindings for sm6150 llcc node.
Change-Id: I4f239f190c01110e59c1081ccf0a57cb1631fb95
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
(cherry picked from commit 4173e882bd59e39d8b698fed8b92417231c98e4e)
Add the Level Shifter's external feedback clock entry to support
the SD card HS50 mode running at 50MHz.
By default, the Sun platforms use the Level Shifter devices with
external feedback clock signal connects back to the MSM in order
for the HS50 mode to work at 50MHz. Without the external feedback
clock, the HS50 mode works at reduced frequency at 37.5MHz.
Change-Id: I56c61411d7f792a389fa85661fce7fa5074e2c9f
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Update power-source to 2 for chipsets to use 1.2 V for BT_EN
CRs-Fixed: 4065538
Change-Id: I72ec6863be8d40b40cdeefbb837f1ac652319173
Signed-off-by: Hemant Gupta <quic_hemantg@quicinc.com>
Reduce the buffer size from 32KB to 16KB and decrease the number
of buffers submitting to the HW to 128 per pipe for effective
utilization and memory optimization.
Change-Id: I709141bd9083570bb18bba0ce13e86956fdfea4a
Signed-off-by: Pavan Kumar M <quic_rpavan@quicinc.com>
WLAN has a requirement to trigger a PBS sequence for XO calibration
for factory testing. To support this, expose a new register under
PMK8550 SDAM2 for clients to write input data into and a new PBS
regulator on which clients can vote to trigger the PBS sequence.
Change-Id: I0e4882d842ea57def4dfdfe4baa5e606a3847f40
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
WLAN has a requirement to trigger a PBS sequence for XO
calibration for factory testing. As part of this feature
expose a new register under PMK8550 SDAM2, which will
be used by PBS for reading XO trims settings.
Change-Id: I620b2d9d0ca6b7452f693ff665ddf995f17e4e2c
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
WLAN has a requirement to trigger a PBS sequence for XO calibration
for factory testing. To support this, expose a new register under
PMK8550 SDAM2 for clients to write input data into and a new PBS
regulator on which clients can vote to trigger the PBS sequence.
Change-Id: Ia314c8cba7a6205943b99e7530990ea6dde8b09c
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
This change removes support for display clock scaling
through mmrm is not supported in kera target.
Change-Id: Idb83968784dcd1e6cabc5bc107a5bd8013612686
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
Correct the port mask of mbhc port.
Since the WCD_SWR_TX DATA0 voltage was incorrect
with default setting, but was correct when
the ADC_LP was running in the swrm bus 9.6mhz,
So copy the SWR_UC0(9.6mhz) to SWR_UC1(4.8mhz).
Change-Id: I3638349a6ebec06b8f4a828498e1285579361e45
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
This change enlarges the iommu dma memory pool range for Milos
Ganges wlan attach.
Change-Id: I81f3db7d230c43d288725c89ac691ab7083fd8b5
CRs-Fixed: 4053659
Add WLAN_EN GPIO definition to be supported through Linux
pinctrl framework.
Using Linux pinctrl framework API add support to control
WLAN_EN GPIO:
1. Read WLAN_EN GPIO value
2. Change WLAN_EN GPIO value
Change-Id: Ic205814b6b38d515b23879673afe76882ad0098b
CRs-Fixed: 4093812
Add ldo-ocp notifier support for tuna for platforms.
Change-Id: I46c1feb2f4ff2da3945f9ad445eb5d99f81f7af4
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Update frequency plan as per the latest recommendation.
updating PS#5 of Ibdd4774022e90ebc0c670ce2cadc071b988698d4
Change-Id: I4aca1dfe66a24e80471ad22a5c1f373d7b2a4e16
Signed-off-by: Rohit Jadhav <quic_rbjadhav@quicinc.com>
Add device tree bindings for arm,arch-cache node.
Change-Id: I46acfdd171e297368d6bedc431af7dd1270909f8
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
Only add wcn-bt-ext for enabling second bt backend for needed dtsi file.
Change-Id: I42ca1840019a9db7d02ac39092f15dd438ea334f
Signed-off-by: MingShu Pang <quic_mpang@quicinc.com>
Remove lpass_bt_swr in ssr devs as bt_swr is disabled in
Kera cdp variant.
Change-Id: Idd149e79b09c1cd3db57100887c3e187bd8420c8
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
